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Searched refs:DwarfRegNum (Results 1 – 17 of 17) sorted by relevance

/external/mesa3d/src/gallium/drivers/radeon/
DAMDILRegisterInfo.td23 def R1 : AMDILReg<1, "r1">, DwarfRegNum<[1]>;
24 def R2 : AMDILReg<2, "r2">, DwarfRegNum<[2]>;
25 def R3 : AMDILReg<3, "r3">, DwarfRegNum<[3]>;
26 def R4 : AMDILReg<4, "r4">, DwarfRegNum<[4]>;
27 def R5 : AMDILReg<5, "r5">, DwarfRegNum<[5]>;
28 def R6 : AMDILReg<6, "r6">, DwarfRegNum<[6]>;
29 def R7 : AMDILReg<7, "r7">, DwarfRegNum<[7]>;
30 def R8 : AMDILReg<8, "r8">, DwarfRegNum<[8]>;
31 def R9 : AMDILReg<9, "r9">, DwarfRegNum<[9]>;
32 def R10 : AMDILReg<10, "r10">, DwarfRegNum<[10]>;
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.td88 def R#i : Ri<i, "r"#i>, DwarfRegNum<[i]>;
91 def R29 : Ri<29, "r29", ["sp"]>, DwarfRegNum<[29]>;
92 def R30 : Ri<30, "r30", ["fp"]>, DwarfRegNum<[30]>;
93 def R31 : Ri<31, "r31", ["lr"]>, DwarfRegNum<[31]>;
97 def D0 : Rd< 0, "r1:0", [R0, R1]>, DwarfRegNum<[32]>;
98 def D1 : Rd< 2, "r3:2", [R2, R3]>, DwarfRegNum<[34]>;
99 def D2 : Rd< 4, "r5:4", [R4, R5]>, DwarfRegNum<[36]>;
100 def D3 : Rd< 6, "r7:6", [R6, R7]>, DwarfRegNum<[38]>;
101 def D4 : Rd< 8, "r9:8", [R8, R9]>, DwarfRegNum<[40]>;
102 def D5 : Rd<10, "r11:10", [R10, R11]>, DwarfRegNum<[42]>;
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/external/llvm/lib/Target/AVR/
DAVRRegisterInfo.td45 def R0 : AVRReg<0, "r0">, DwarfRegNum<[0]>;
46 def R1 : AVRReg<1, "r1">, DwarfRegNum<[1]>;
47 def R2 : AVRReg<2, "r2">, DwarfRegNum<[2]>;
48 def R3 : AVRReg<3, "r3">, DwarfRegNum<[3]>;
49 def R4 : AVRReg<4, "r4">, DwarfRegNum<[4]>;
50 def R5 : AVRReg<5, "r5">, DwarfRegNum<[5]>;
51 def R6 : AVRReg<6, "r6">, DwarfRegNum<[6]>;
52 def R7 : AVRReg<7, "r7">, DwarfRegNum<[7]>;
53 def R8 : AVRReg<8, "r8">, DwarfRegNum<[8]>;
54 def R9 : AVRReg<9, "r9">, DwarfRegNum<[9]>;
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/external/llvm/lib/Target/Sparc/
DSparcRegisterInfo.td66 def Y : SparcCtrlReg<0, "Y">, DwarfRegNum<[64]>;
122 def G0 : Ri< 0, "G0">, DwarfRegNum<[0]>;
123 def G1 : Ri< 1, "G1">, DwarfRegNum<[1]>;
124 def G2 : Ri< 2, "G2">, DwarfRegNum<[2]>;
125 def G3 : Ri< 3, "G3">, DwarfRegNum<[3]>;
126 def G4 : Ri< 4, "G4">, DwarfRegNum<[4]>;
127 def G5 : Ri< 5, "G5">, DwarfRegNum<[5]>;
128 def G6 : Ri< 6, "G6">, DwarfRegNum<[6]>;
129 def G7 : Ri< 7, "G7">, DwarfRegNum<[7]>;
130 def O0 : Ri< 8, "O0">, DwarfRegNum<[8]>;
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/external/llvm/lib/Target/XCore/
DXCoreRegisterInfo.td26 def R0 : Ri< 0, "r0">, DwarfRegNum<[0]>;
27 def R1 : Ri< 1, "r1">, DwarfRegNum<[1]>;
28 def R2 : Ri< 2, "r2">, DwarfRegNum<[2]>;
29 def R3 : Ri< 3, "r3">, DwarfRegNum<[3]>;
30 def R4 : Ri< 4, "r4">, DwarfRegNum<[4]>;
31 def R5 : Ri< 5, "r5">, DwarfRegNum<[5]>;
32 def R6 : Ri< 6, "r6">, DwarfRegNum<[6]>;
33 def R7 : Ri< 7, "r7">, DwarfRegNum<[7]>;
34 def R8 : Ri< 8, "r8">, DwarfRegNum<[8]>;
35 def R9 : Ri< 9, "r9">, DwarfRegNum<[9]>;
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/external/llvm/lib/Target/Mips/
DMipsRegisterInfo.td88 def ZERO : MipsGPRReg< 0, "zero">, DwarfRegNum<[0]>;
89 def AT : MipsGPRReg< 1, "1">, DwarfRegNum<[1]>;
90 def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>;
91 def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>;
92 def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[4]>;
93 def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>;
94 def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>;
95 def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>;
96 def T0 : MipsGPRReg< 8, "8">, DwarfRegNum<[8]>;
97 def T1 : MipsGPRReg< 9, "9">, DwarfRegNum<[9]>;
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/external/llvm/lib/Target/X86/
DX86RegisterInfo.td105 def EAX : X86Reg<"eax", 0, [AX]>, DwarfRegNum<[-2, 0, 0]>;
106 def EDX : X86Reg<"edx", 2, [DX]>, DwarfRegNum<[-2, 2, 2]>;
107 def ECX : X86Reg<"ecx", 1, [CX]>, DwarfRegNum<[-2, 1, 1]>;
108 def EBX : X86Reg<"ebx", 3, [BX]>, DwarfRegNum<[-2, 3, 3]>;
109 def ESI : X86Reg<"esi", 6, [SI]>, DwarfRegNum<[-2, 6, 6]>;
110 def EDI : X86Reg<"edi", 7, [DI]>, DwarfRegNum<[-2, 7, 7]>;
111 def EBP : X86Reg<"ebp", 5, [BP]>, DwarfRegNum<[-2, 4, 5]>;
112 def ESP : X86Reg<"esp", 4, [SP]>, DwarfRegNum<[-2, 5, 4]>;
113 def EIP : X86Reg<"eip", 0, [IP]>, DwarfRegNum<[-2, 8, 8]>;
129 def RAX : X86Reg<"rax", 0, [EAX]>, DwarfRegNum<[0, -2, -2]>;
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/external/llvm/lib/Target/BPF/
DBPFRegisterInfo.td22 def R0 : Ri< 0, "r0">, DwarfRegNum<[0]>;
23 def R1 : Ri< 1, "r1">, DwarfRegNum<[1]>;
24 def R2 : Ri< 2, "r2">, DwarfRegNum<[2]>;
25 def R3 : Ri< 3, "r3">, DwarfRegNum<[3]>;
26 def R4 : Ri< 4, "r4">, DwarfRegNum<[4]>;
27 def R5 : Ri< 5, "r5">, DwarfRegNum<[5]>;
28 def R6 : Ri< 6, "r6">, DwarfRegNum<[6]>;
29 def R7 : Ri< 7, "r7">, DwarfRegNum<[7]>;
30 def R8 : Ri< 8, "r8">, DwarfRegNum<[8]>;
31 def R9 : Ri< 9, "r9">, DwarfRegNum<[9]>;
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/external/llvm/lib/Target/AArch64/
DAArch64RegisterInfo.td55 def W0 : AArch64Reg<0, "w0" >, DwarfRegNum<[0]>;
56 def W1 : AArch64Reg<1, "w1" >, DwarfRegNum<[1]>;
57 def W2 : AArch64Reg<2, "w2" >, DwarfRegNum<[2]>;
58 def W3 : AArch64Reg<3, "w3" >, DwarfRegNum<[3]>;
59 def W4 : AArch64Reg<4, "w4" >, DwarfRegNum<[4]>;
60 def W5 : AArch64Reg<5, "w5" >, DwarfRegNum<[5]>;
61 def W6 : AArch64Reg<6, "w6" >, DwarfRegNum<[6]>;
62 def W7 : AArch64Reg<7, "w7" >, DwarfRegNum<[7]>;
63 def W8 : AArch64Reg<8, "w8" >, DwarfRegNum<[8]>;
64 def W9 : AArch64Reg<9, "w9" >, DwarfRegNum<[9]>;
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/external/llvm/lib/Target/ARM/
DARMRegisterInfo.td60 def R0 : ARMReg< 0, "r0">, DwarfRegNum<[0]>;
61 def R1 : ARMReg< 1, "r1">, DwarfRegNum<[1]>;
62 def R2 : ARMReg< 2, "r2">, DwarfRegNum<[2]>;
63 def R3 : ARMReg< 3, "r3">, DwarfRegNum<[3]>;
64 def R4 : ARMReg< 4, "r4">, DwarfRegNum<[4]>;
65 def R5 : ARMReg< 5, "r5">, DwarfRegNum<[5]>;
66 def R6 : ARMReg< 6, "r6">, DwarfRegNum<[6]>;
67 def R7 : ARMReg< 7, "r7">, DwarfRegNum<[7]>;
70 def R8 : ARMReg< 8, "r8">, DwarfRegNum<[8]>;
71 def R9 : ARMReg< 9, "r9">, DwarfRegNum<[9]>;
[all …]
/external/llvm/lib/Target/PowerPC/
DPPCRegisterInfo.td104 def R#Index : GPR<Index, "r"#Index>, DwarfRegNum<[-2, Index]>;
110 DwarfRegNum<[Index, -2]>;
116 DwarfRegNum<[!add(Index, 32), !add(Index, 32)]>;
127 DwarfRegNum<[!add(Index, 32), !add(Index, 32)]>;
133 DwarfRegNum<[!add(Index, 77), !add(Index, 77)]>;
194 def CR0 : CR<0, "cr0", [CR0LT, CR0GT, CR0EQ, CR0UN]>, DwarfRegNum<[68, 68]>;
195 def CR1 : CR<1, "cr1", [CR1LT, CR1GT, CR1EQ, CR1UN]>, DwarfRegNum<[69, 69]>;
196 def CR2 : CR<2, "cr2", [CR2LT, CR2GT, CR2EQ, CR2UN]>, DwarfRegNum<[70, 70]>;
197 def CR3 : CR<3, "cr3", [CR3LT, CR3GT, CR3EQ, CR3UN]>, DwarfRegNum<[71, 71]>;
198 def CR4 : CR<4, "cr4", [CR4LT, CR4GT, CR4EQ, CR4UN]>, DwarfRegNum<[72, 72]>;
[all …]
/external/llvm/include/llvm/CodeGen/
DStackMaps.h152 unsigned short DwarfRegNum; member
155 LiveOutReg() : Reg(0), DwarfRegNum(0), Size(0) {} in LiveOutReg()
156 LiveOutReg(unsigned short Reg, unsigned short DwarfRegNum, in LiveOutReg()
158 : Reg(Reg), DwarfRegNum(DwarfRegNum), Size(Size) {} in LiveOutReg()
/external/llvm/lib/CodeGen/
DStackMaps.cpp143 unsigned DwarfRegNum = getDwarfRegNum(MOI->getReg(), TRI); in parseOperand() local
144 unsigned LLVMRegNum = TRI->getLLVMRegNum(DwarfRegNum, false); in parseOperand()
149 Locs.emplace_back(Location::Register, RC->getSize(), DwarfRegNum, Offset); in parseOperand()
222 OS << "\t[encoding: .short " << LO.DwarfRegNum << ", .byte 0, .byte " in print()
232 unsigned DwarfRegNum = getDwarfRegNum(Reg, TRI); in createLiveOutReg() local
234 return LiveOutReg(Reg, DwarfRegNum, Size); in createLiveOutReg()
257 return LHS.DwarfRegNum < RHS.DwarfRegNum; in parseRegisterLiveOutMask()
262 if (I->DwarfRegNum != II->DwarfRegNum) { in parseRegisterLiveOutMask()
510 OS.EmitIntValue(LO.DwarfRegNum, 2); in emitCallsiteEntries()
/external/llvm/lib/Target/SystemZ/
DSystemZRegisterInfo.td81 DwarfRegNum<[I]>;
194 DwarfRegNum<[!cast<DwarfMapping>("F"#I#"Dwarf").Id]>;
199 DwarfRegNum<[!cast<DwarfMapping>("F"#I#"Dwarf").Id]>;
228 DwarfRegNum<[!cast<DwarfMapping>("F"#I#"Dwarf").Id]>;
/external/llvm/docs/
DWritingAnLLVMBackend.rst368 def AL : Register<"AL">, DwarfRegNum<[0, 0, 0]>;
370 This defines the register ``AL`` and assigns it values (with ``DwarfRegNum``)
372 register. For register ``AL``, ``DwarfRegNum`` takes an array of 3 values
459 def G0 : Ri< 0, "G0">, DwarfRegNum<[0]>;
460 def G1 : Ri< 1, "G1">, DwarfRegNum<[1]>;
462 def F0 : Rf< 0, "F0">, DwarfRegNum<[32]>;
463 def F1 : Rf< 1, "F1">, DwarfRegNum<[33]>;
465 def D0 : Rd< 0, "F0", [F0, F1]>, DwarfRegNum<[32]>;
466 def D1 : Rd< 2, "F2", [F2, F3]>, DwarfRegNum<[34]>;
/external/llvm/lib/Target/AMDGPU/
DSIRegisterInfo.td14 DwarfRegNum<[!cast<int>(HWEncoding)]> {
/external/llvm/include/llvm/Target/
DTarget.td291 // DwarfRegNum - This class provides a mapping of the llvm register enumeration
295 class DwarfRegNum<list<int> Numbers> {