| /external/llvm/lib/Target/PowerPC/ |
| D | PPCTargetTransformInfo.cpp | 319 if (ISD == ISD::INSERT_VECTOR_ELT) in getVectorInstrCost()
327 ISD == ISD::INSERT_VECTOR_ELT) in getVectorInstrCost()
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| D | README_ALTIVEC.txt | 319 Currently EXTRACT_VECTOR_ELT and INSERT_VECTOR_ELT are type-legal only
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| D | PPCISelLowering.cpp | 471 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand); in PPCTargetLowering()
679 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f64, Expand); in PPCTargetLowering()
729 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f32, Expand); in PPCTargetLowering()
771 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4i1, Expand); in PPCTargetLowering()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 271 INSERT_VECTOR_ELT, enumerator
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDILISelLowering.cpp | 385 ISD::INSERT_VECTOR_ELT, in LowerBUILD_VECTOR()
396 ISD::INSERT_VECTOR_ELT, in LowerBUILD_VECTOR()
407 ISD::INSERT_VECTOR_ELT, in LowerBUILD_VECTOR()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | R600ISelLowering.cpp | 163 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i32, Custom); in R600TargetLowering()
164 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f32, Custom); in R600TargetLowering()
165 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); in R600TargetLowering()
166 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); in R600TargetLowering()
172 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT); in R600TargetLowering()
593 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); in LowerOperation()
948 SDValue Insert = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, Op.getValueType(), in LowerINSERT_VECTOR_ELT()
1882 case ISD::INSERT_VECTOR_ELT: { in PerformDAGCombine()
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| D | SIISelLowering.cpp | 213 case ISD::INSERT_VECTOR_ELT: in SITargetLowering()
237 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote); in SITargetLowering()
238 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v4i32); in SITargetLowering()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeTypesGeneric.cpp | 446 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, NewVec, Lo, Idx); in ExpandOp_INSERT_VECTOR_ELT()
450 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, NewVec, Hi, Idx); in ExpandOp_INSERT_VECTOR_ELT()
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| D | LegalizeVectorTypes.cpp | 59 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break; in ScalarizeVectorResult()
605 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break; in SplitVectorResult()
932 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, in SplitVecRes_INSERT_VECTOR_ELT()
936 DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt, in SplitVecRes_INSERT_VECTOR_ELT()
2007 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break; in WidenVectorResult()
2239 ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp, ConcatOps[OpIdx], in WidenVecRes_BinaryCanTrap()
2714 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N), in WidenVecRes_INSERT_VECTOR_ELT()
3363 ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i], in BuildVectorFromScalar()
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| D | SelectionDAGDumper.cpp | 217 case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt"; in getOperationName()
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| D | LegalizeIntegerTypes.cpp | 96 case ISD::INSERT_VECTOR_ELT: in PromoteIntegerResult()
887 case ISD::INSERT_VECTOR_ELT: in PromoteIntegerOperand()
2662 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break; in ExpandIntegerOperand()
3262 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NOutVT, in PromoteIntRes_INSERT_VECTOR_ELT()
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| D | LegalizeDAG.cpp | 3207 case ISD::INSERT_VECTOR_ELT: in ExpandNode()
4220 Node->getOpcode() == ISD::INSERT_VECTOR_ELT) { in PromoteNode()
4533 case ISD::INSERT_VECTOR_ELT: { in PromoteNode()
4576 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, SL, NVT, in PromoteNode()
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| D | DAGCombiner.cpp | 1435 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); in visit()
12031 if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT && InVec.hasOneUse() in visitINSERT_VECTOR_ELT()
12037 SDValue NewOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N), VT, in visitINSERT_VECTOR_ELT()
12040 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(InVec.getNode()), in visitINSERT_VECTOR_ELT()
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| D | SelectionDAG.cpp | 3675 if (N1.getOpcode() == ISD::INSERT_VECTOR_ELT) { in getNode()
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| D | SelectionDAGBuilder.cpp | 2680 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(), in visitInsertElement()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 101 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in addTypeForNEON()
623 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT); in ARMTargetLowering()
1469 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, in LowerCallResult()
1483 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, in LowerCallResult()
3156 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, in LowerFormalArguments()
3159 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, in LowerFormalArguments()
5476 DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DAG.getUNDEF(VT), in LowerBUILD_VECTOR()
5495 N = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Ops); in LowerBUILD_VECTOR()
5559 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx); in LowerBUILD_VECTOR()
6140 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val, in LowerCONCAT_VECTORS()
[all …]
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1767 ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT, in HexagonTargetLowering()
1793 setOperationAction(ISD::INSERT_VECTOR_ELT, NativeVT, Custom); in HexagonTargetLowering()
2491 SDValue Width = DAG.getConstant(Op.getOpcode() == ISD::INSERT_VECTOR_ELT ? in LowerINSERT_VECTOR()
2585 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR(Op, DAG); in LowerOperation()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 700 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand); in X86TargetLowering()
791 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand); in X86TargetLowering()
858 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); in X86TargetLowering()
859 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); in X86TargetLowering()
860 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); in X86TargetLowering()
906 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); in X86TargetLowering()
910 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); in X86TargetLowering()
1009 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); in X86TargetLowering()
1010 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); in X86TargetLowering()
1011 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); in X86TargetLowering()
[all …]
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 506 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT); in AArch64TargetLowering()
663 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getSimpleVT(), Custom); in addTypeForNEON()
2295 case ISD::INSERT_VECTOR_ELT: in LowerOperation()
5608 ISD::INSERT_VECTOR_ELT, dl, VT, DstVec, in LowerVECTOR_SHUFFLE()
6296 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx); in LowerBUILD_VECTOR()
6345 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx); in LowerBUILD_VECTOR()
6356 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Unknown opcode!"); in LowerINSERT_VECTOR_ELT()
6381 SDValue Node = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, WideTy, WideVec, in LowerINSERT_VECTOR_ELT()
8547 if (StVal.getOpcode() != ISD::INSERT_VECTOR_ELT) in replaceSplatVectorStore()
8560 if (NextInsertElt.getOpcode() != ISD::INSERT_VECTOR_ELT) in replaceSplatVectorStore()
[all …]
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 302 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Legal); in SystemZTargetLowering()
384 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); in SystemZTargetLowering()
385 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); in SystemZTargetLowering()
4061 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, Result, Elems[I], in buildVector()
4176 return DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, in lowerSCALAR_TO_VECTOR()
4206 SDValue Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, IntVecVT, in lowerINSERT_VECTOR_ELT()
4401 case ISD::INSERT_VECTOR_ELT: in LowerOperation()
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| D | SystemZISelDAGToDAG.cpp | 1249 case ISD::INSERT_VECTOR_ELT: { in Select()
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| D | SystemZOperators.td | 193 def z_vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 257 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal); in addMSAIntType()
306 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal); in addMSAFloatType()
1942 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2410 Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector, in lowerBUILD_VECTOR()
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 414 def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>;
540 def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
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| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 1601 case InsertElement: return ISD::INSERT_VECTOR_ELT; in InstructionOpcodeToISD()
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