| /external/llvm/lib/CodeGen/ |
| D | TargetSchedule.cpp | 35 return EnableSchedItins && !InstrItins.isEmpty(); in hasInstrItineraries()
59 STI->initInstrItins(InstrItins); in init()
79 int UOps = InstrItins.getNumMicroOps(MI->getDesc().getSchedClass()); in getNumMicroOps()
80 return (UOps >= 0) ? UOps : TII->getNumMicroOps(&InstrItins, MI); in getNumMicroOps()
164 OperLatency = TII->getOperandLatency(&InstrItins, DefMI, DefOperIdx, in computeOperandLatency()
169 OperLatency = InstrItins.getOperandCycle(DefClass, DefOperIdx); in computeOperandLatency()
175 unsigned InstrLatency = TII->getInstrLatency(&InstrItins, DefMI); in computeOperandLatency()
257 return TII->getInstrLatency(&InstrItins, MI); in computeInstrLatency()
|
| D | DFAPacketizer.cpp | 59 InstrItins(I), CurrentState(0), DFAStateInputTable(SIT), in DFAPacketizer()
99 for (const InstrStage *IS = InstrItins->beginStage(InsnClass), in getInsnInput()
100 *IE = InstrItins->endStage(InsnClass); IS != IE; ++IS, ++i) { in getInsnInput()
|
| D | PostRASchedulerList.cpp | 201 const InstrItineraryData *InstrItins = in SchedulePostRATDList() local
205 InstrItins, this); in SchedulePostRATDList()
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDGPUSubtarget.h | 40 InstrItineraryData InstrItins; variable
46 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; } in getInstrItineraryData()
|
| D | AMDGPUTargetMachine.h | 37 const InstrItineraryData* InstrItins; variable
62 return InstrItins; in getInstrItineraryData()
|
| D | AMDGPUSubtarget.cpp | 25 InstrItins = getInstrItineraryForCPU(CPU); in AMDGPUSubtarget()
|
| D | AMDGPUTargetMachine.cpp | 54 InstrItins(&Subtarget.getInstrItineraryData()), in AMDGPUTargetMachine()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonSubtarget.h | 56 InstrItineraryData InstrItins; variable
66 return &InstrItins; in getInstrItineraryData()
|
| D | HexagonSubtarget.cpp | 100 InstrItins = getInstrItineraryForCPU(CPUString); in HexagonSubtarget()
|
| /external/llvm/include/llvm/CodeGen/ |
| D | TargetSchedule.h | 36 InstrItineraryData InstrItins; variable
80 return &InstrItins; in getInstrItineraries()
|
| D | DFAPacketizer.h | 75 const InstrItineraryData *InstrItins; variable
117 const InstrItineraryData *getInstrItins() const { return InstrItins; } in getInstrItins()
|
| D | ResourcePriorityQueue.h | 63 const InstrItineraryData* InstrItins; variable
|
| /external/llvm/lib/MC/ |
| D | MCSubtargetInfo.cpp | 108 void MCSubtargetInfo::initInstrItins(InstrItineraryData &InstrItins) const { in initInstrItins()
109 InstrItins = InstrItineraryData(getSchedModel(), Stages, OperandCycles, in initInstrItins()
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUSubtarget.h | 95 InstrItineraryData InstrItins; variable
117 return &InstrItins; in getInstrItineraryData()
|
| D | AMDGPUSubtarget.cpp | 79 InstrItins(getInstrItineraryForCPU(GPU)), TargetTriple(TT) { in AMDGPUSubtarget()
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCSubtarget.h | 76 InstrItineraryData InstrItins; variable
160 return &InstrItins; in getInstrItineraryData()
|
| D | PPCSubtarget.cpp | 120 InstrItins = getInstrItineraryForCPU(CPUName); in initSubtargetFeatures()
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsSubtarget.h | 145 InstrItineraryData InstrItins; variable
307 return &InstrItins; in getInstrItineraryData()
|
| D | MipsSubtarget.cpp | 150 InstrItins = getInstrItineraryForCPU(CPUName); in initializeSubtargetDependencies()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMSubtarget.h | 250 InstrItineraryData InstrItins; variable
474 return &InstrItins; in getInstrItineraryData()
|
| /external/llvm/lib/Target/X86/ |
| D | X86Subtarget.h | 247 InstrItineraryData InstrItins; variable
536 return &InstrItins; in getInstrItineraryData()
|
| D | X86Subtarget.cpp | 211 InstrItins = getInstrItineraryForCPU(CPUName); in initSubtargetFeatures()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGSDNodes.cpp | 50 InstrItins(mf.getSubtarget().getInstrItineraryData()) {} in ScheduleDAGSDNodes()
608 if (!InstrItins || InstrItins->isEmpty()) { in computeLatency()
622 SU->Latency += TII->getInstrLatency(InstrItins, N); in computeLatency()
638 int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx); in computeOperandLatency()
|
| D | ScheduleDAGSDNodes.h | 40 const InstrItineraryData *InstrItins; variable
|
| /external/llvm/include/llvm/MC/ |
| D | MCSubtargetInfo.h | 159 void initInstrItins(InstrItineraryData &InstrItins) const;
|