| /external/llvm/lib/CodeGen/ |
| D | ExpandPostRAPseudos.cpp | 103 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerSubregToReg()
114 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerSubregToReg()
141 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerCopy()
156 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerCopy()
|
| D | LiveRangeEdit.cpp | 307 MI->setDesc(TII.get(TargetOpcode::KILL)); in eliminateDeadDef()
|
| D | InlineSpiller.cpp | 808 MI->setDesc(TII.get(TargetOpcode::KILL)); in eliminateRedundantSpills()
|
| /external/llvm/test/CodeGen/Mips/ |
| D | delay-slot-kill.ll | 5 ; Currently, the following IR assembly generates a KILL instruction between
7 ; delay slot filler ignores such KILL instructions by filling the slot of the
|
| /external/compiler-rt/test/asan/TestCases/Android/ |
| D | coverage-android.cc | 115 #ifdef KILL in bar()
|
| /external/mksh/src/ |
| D | signames.inc | 12 { "KILL", 9 },
|
| /external/llvm/include/llvm/Target/ |
| D | TargetOpcodes.h | 35 KILL = 5, enumerator
|
| /external/strace/tests/ |
| D | ppoll.expected | 2 …d=0, events=POLLOUT(\|POLLWRNORM)?\|POLLWRBAND\}\], 2, \{0, 999\}, ~\[HUP KILL STOP[^]]*\], (4|8|1…
|
| D | ppoll-v.expected | 2 …d=0, events=POLLOUT(\|POLLWRNORM)?\|POLLWRBAND\}\], 2, \{0, 999\}, ~\[HUP KILL STOP[^]]*\], (4|8|1…
|
| /external/autotest/client/site_tests/platform_DaemonsRespawn/ |
| D | test_respawn.sh | 66 kill -KILL $PID
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | R600EmitClauseMarkers.cpp | 48 case AMDGPU::KILL: in OccupiedDwords()
94 case AMDGPU::KILL: in IsTrivialInst()
|
| D | R600ControlFlowFinalizer.cpp | 227 case AMDGPU::KILL: in IsTrivialInst()
|
| /external/llvm/test/CodeGen/MIR/ARM/ |
| D | sched-it-debug-nodes.mir | 29 ; accidentally being marked as KILL. The DBG_VALUE node gets introduced in
32 ; debug value as KILL'ed, resulting in a DEBUG_VALUE node changing codegen! (or
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonNewValueJump.cpp | 132 if (II->getOpcode() == TargetOpcode::KILL) in INITIALIZE_PASS_DEPENDENCY()
196 if (MII->getOpcode() == TargetOpcode::KILL || in commonChecksToProhibitNewValueJump()
|
| D | HexagonMachineScheduler.cpp | 110 case TargetOpcode::KILL: in reserveResources()
|
| /external/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| D | R600MCCodeEmitter.cpp | 96 MI.getOpcode() == AMDGPU::KILL) { in encodeInstruction()
|
| /external/llvm/include/llvm/CodeGen/ |
| D | MachineInstr.h | 765 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
822 case TargetOpcode::KILL:
|
| /external/llvm/lib/Target/MSP430/ |
| D | MSP430InstrInfo.cpp | 303 case TargetOpcode::KILL: in GetInstSizeInBytes()
|
| /external/libvncserver/webclients/java-applet/ssl/ |
| D | ss_vncviewer | 811 kill -KILL "$pssh" 2>/dev/null
819 kill -KILL "$stunnel_pid" 2>/dev/null
827 kill -KILL "$dsm_pid" 2>/dev/null
|
| /external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
| D | R600MCCodeEmitter.cpp | 158 MI.getOpcode() == AMDGPU::KILL) { in EncodeInstruction()
|
| /external/bison/tests/ |
| D | local.at | 104 [m4_divert_text([KILL],
239 [m4_divert_text([KILL],
|
| /external/toybox/lib/ |
| D | lib.c | 735 SIGNIFY(FPE), SIGNIFY(HUP), SIGNIFY(ILL), SIGNIFY(INT), SIGNIFY(KILL),
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 2645 /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 }, in ARMEmitIntExt()
2653 /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 }, in ARMEmitIntExt()
2680 assert(ARM::KILL != Opc && "Invalid table entry"); in ARMEmitIntExt()
|
| /external/bison/data/m4sugar/ |
| D | m4sugar.m4 | 1391 # KILL is only used to suppress output.
1392 m4_define([_m4_divert(KILL)], -1)
3259 m4_divert_push([KILL])
3292 m4_divert([KILL])
3297 # KILL as the bottom of the diversion stack.
3300 ]m4_divert_stack)])_m4_popdef([_m4_divert_stack])m4_divert_push([KILL])])
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.cpp | 568 BuildMI(MBB, II, dl, TII.get(TargetOpcode::KILL), in lowerCRBitSpilling()
|