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Searched refs:M0 (Results 1 – 25 of 74) sorted by relevance

123

/external/mesa3d/src/mesa/sparc/
Dsparc_matrix.h35 #define M0 %f16 macro
53 ldd [BASE + ( 0 * 0x4)], M0; \
59 ldd [BASE + ( 0 * 0x4)], M0; \
63 ld [BASE + ( 0 * 0x4)], M0; \
67 ldd [BASE + ( 0 * 0x4)], M0; \
73 ld [BASE + ( 0 * 0x4)], M0; \
78 ld [BASE + ( 0 * 0x4)], M0; \
82 ldd [BASE + ( 0 * 0x4)], M0; \
90 ld [BASE + ( 0 * 0x4)], M0; \
95 ldd [BASE + ( 0 * 0x4)], M0; \
[all …]
Dxform.S82 fmuls %f0, M0, %f1 ! FGM Group 1-cycle stall on %f0
86 fmuls %f8, M0, %f9 ! FGM Group f1 available
115 fmuls %f0, M0, %f1 ! FGM Group 1-cycle stall on %f0
197 fmuls %f0, M0, %f1 ! FGM Group
199 fmuls %f8, M0, %f9 ! FGM Group
218 fmuls %f0, M0, %f1
251 fmuls %f0, M0, %f1 ! FGM Group
252 fmuls %f4, M0, %f5 ! FGM Group
268 fmuls %f0, M0, %f1
299 fmuls %f0, M0, %f1 ! FGM Group
[all …]
Dnorm.S60 fmuls %f0, M0, %f3 ! FGM Group
104 fmuls M0, %f15, M0
125 fmuls %f0, M0, %f3 ! FGM Group
199 fmuls %f0, M0, %f3 ! FGM Group
231 fmuls M0, %f15, M0
246 fmuls %f0, M0, %f3 ! FGM Group
291 fmuls M0, %f15, M0
305 fmuls %f0, M0, %f3 ! FGM Group
342 fmuls M0, %f15, M0
358 fmuls %f0, M0, %f3 ! FGM Group
[all …]
/external/opencv3/modules/videostab/src/
Dmotion_stabilizing.cpp275 Mat_<float> M0 = at(t,M); in stabilize() local
286 set(r, c, M0(0,0)); set(r, c+1, M0(1,0)); in stabilize()
287 set(r+1, c, M0(0,1)); set(r+1, c+1, M0(1,1)); in stabilize()
288 set(r+2, c, M0(0,2)); set(r+2, c+1, M0(1,2)); set(r+2, c+2, 1); in stabilize()
289 set(r+3, c, M0(1,0)); set(r+3, c+1, -M0(0,0)); in stabilize()
290 set(r+4, c, M0(1,1)); set(r+4, c+1, -M0(0,1)); in stabilize()
291 set(r+5, c, M0(1,2)); set(r+5, c+1, -M0(0,2)); set(r+5, c+3, 1); in stabilize()
308 Mat_<float> M0 = at(t,M); in stabilize() local
319 set(r, c, M0(0,0)); set(r, c+1, M0(1,0)); in stabilize()
320 set(r+1, c, M0(0,1)); set(r+1, c+1, M0(1,1)); in stabilize()
[all …]
/external/llvm/test/CodeGen/ARM/
Datomic-op.ll4 …iple=thumbv6-apple-ios -verify-machineinstrs -mcpu=cortex-m0 | FileCheck %s --check-prefix=CHECK-M0
33 ; CHECK-M0: bl ___sync_fetch_and_add_4
42 ; CHECK-M0: bl ___sync_fetch_and_sub_4
51 ; CHECK-M0: bl ___sync_fetch_and_add_4
60 ; CHECK-M0: bl ___sync_fetch_and_sub_4
69 ; CHECK-M0: bl ___sync_fetch_and_and_4
78 ; CHECK-M0: bl ___sync_fetch_and_or_4
87 ; CHECK-M0: bl ___sync_fetch_and_xor_4
96 ; CHECK-M0: bl ___sync_fetch_and_min_4
106 ; CHECK-M0: bl ___sync_fetch_and_min_4
[all …]
Dbuild-attributes.ll62 …thumbv6m-linux-gnueabi -mcpu=cortex-m0 -mattr=+strict-align | FileCheck %s --check-prefix=CORTEX-M0
63 …infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M0-FAST
735 ; CORTEX-M0: .cpu cortex-m0
736 ; CORTEX-M0: .eabi_attribute 6, 12
737 ; CORTEX-M0-NOT: .eabi_attribute 7
738 ; CORTEX-M0: .eabi_attribute 8, 0
739 ; CORTEX-M0: .eabi_attribute 9, 1
740 ; CORTEX-M0-NOT: .eabi_attribute 19
742 ; CORTEX-M0: .eabi_attribute 20, 1
743 ; CORTEX-M0: .eabi_attribute 21, 1
[all …]
/external/llvm/unittests/Support/
DCommandLineTest.cpp54 explicit StackOption(const M0t &M0) : Base(M0) {} in StackOption() argument
58 StackOption(const M0t &M0, const M1t &M1) : Base(M0, M1) {} in StackOption() argument
62 StackOption(const M0t &M0, const M1t &M1, const M2t &M2) : Base(M0, M1, M2) {} in StackOption() argument
66 StackOption(const M0t &M0, const M1t &M1, const M2t &M2, const M3t &M3) in StackOption() argument
67 : Base(M0, M1, M2, M3) {} in StackOption()
/external/mesa3d/src/gallium/drivers/radeon/
DSIISelLowering.cpp153 unsigned M0 = MRI.createVirtualRegister(&AMDGPU::M0RegRegClass); in LowerSI_INTERP() local
161 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_MOV_B32), M0) in LowerSI_INTERP()
168 .addReg(M0); in LowerSI_INTERP()
176 .addReg(M0); in LowerSI_INTERP()
189 unsigned M0 = MRI.createVirtualRegister(&AMDGPU::M0RegRegClass); in LowerSI_INTERP_CONST() local
191 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_MOV_B32), M0) in LowerSI_INTERP_CONST()
198 .addReg(M0); in LowerSI_INTERP_CONST()
DSIRegisterInfo.cpp36 case AMDGPU::M0: return 124; in getBinaryCode()
/external/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.td122 // C6 and C7 can also be M0 and M1, but register names must be unique, even
124 def M0 : Mx<0, "m0">, DwarfRegNum<[72]>;
141 def C6 : Rc<6, "c6", [], [M0]>, DwarfRegNum<[73]>;
246 def ModRegs : RegisterClass<"Hexagon", [i32], 32, (add M0, M1)>;
252 M0, M1, C6, C7, CS0, CS1, UPCL, UPCH,
263 M0, M1,
DHexagonExpandPredSpillCode.cpp115 NewMI->addOperand(MachineOperand::CreateReg(Hexagon::M0, in runOnMachineFunction()
159 NewMI->addOperand(MachineOperand::CreateReg(Hexagon::M0, in runOnMachineFunction()
199 NewMI->addOperand(MachineOperand::CreateReg(Hexagon::M0, in runOnMachineFunction()
235 NewMI->addOperand(MachineOperand::CreateReg(Hexagon::M0, in runOnMachineFunction()
/external/llvm/lib/Target/AMDGPU/
DSILowerControlFlow.cpp339 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_ADD_I32), AMDGPU::M0) in LoadM0()
343 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0) in LoadM0()
362 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0) in LoadM0()
367 .addReg(AMDGPU::M0) in LoadM0()
375 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_ADD_I32), AMDGPU::M0) in LoadM0()
376 .addReg(AMDGPU::M0) in LoadM0()
DSILoadStoreOptimizer.cpp276 LiveRange &M0Range = LIS->getRegUnit(*MCRegUnitIterator(AMDGPU::M0, TRI)); in mergeRead2Pair()
344 LiveRange &M0Range = LIS->getRegUnit(*MCRegUnitIterator(AMDGPU::M0, TRI)); in mergeWrite2Pair()
DSIISelLowering.cpp1127 SDNode *M0 = DAG.getMachineNode(AMDGPU::S_MOV_B32, DL, V.getValueType(), V); in copyToM0() local
1128 return DAG.getCopyToReg(Chain, DL, DAG.getRegister(AMDGPU::M0, MVT::i32), in copyToM0()
1129 SDValue(M0, 0), SDValue()); // Glue in copyToM0()
1245 SDValue M0 = copyToM0(DAG, DAG.getEntryNode(), DL, Op.getOperand(3)); in LowerINTRINSIC_WO_CHAIN() local
1246 SDValue Glue = M0.getValue(1); in LowerINTRINSIC_WO_CHAIN()
1261 SDValue M0 = copyToM0(DAG, DAG.getEntryNode(), DL, Op.getOperand(3)); in LowerINTRINSIC_WO_CHAIN() local
1262 SDValue Glue = M0.getValue(1); in LowerINTRINSIC_WO_CHAIN()
1271 SDValue M0 = copyToM0(DAG, DAG.getEntryNode(), DL, Op.getOperand(4)); in LowerINTRINSIC_WO_CHAIN() local
1272 SDValue Glue = M0.getValue(1); in LowerINTRINSIC_WO_CHAIN()
1277 SDValue M0 = copyToM0(DAG, DAG.getEntryNode(), DL, Op.getOperand(5)); in LowerINTRINSIC_WO_CHAIN() local
[all …]
DSIRegisterInfo.td45 def M0 : SIReg <"m0", 124>;
197 (add SGPR_32, M0, VCC_LO, VCC_HI, EXEC_LO, EXEC_HI, FLAT_SCR_LO, FLAT_SCR_HI)
/external/boringssl/src/crypto/ec/asm/
Dp256-x86_64-asm.pl1096 my ($M0,$T0a,$T0b,$T0c,$T0d,$T0e,$T0f,$TMP0)=map("%xmm$_",(8..15));
1138 movdqa $ONE, $M0
1144 movdqa $M0, $TMP0
1145 paddd $ONE, $M0
1225 movdqa .LOne(%rip), $M0
1233 movdqa $M0, $ONE
1238 movdqa $M0, $TMP0
1239 paddd $ONE, $M0
1287 my ($M0,$T0a,$T0b,$T0c,$TMP0)=map("%ymm$_",(5..9));
1321 vmovdqa .LOne(%rip), $M0
[all …]
/external/boringssl/src/crypto/poly1305/
Dpoly1305_vec.c289 xmmi M0, M1, M2, M3, M4; in poly1305_blocks() local
352 M0 = _mm_and_si128(MMASK, T5); in poly1305_blocks()
360 T5 = _mm_mul_epu32(M0, p->R20.v); in poly1305_blocks()
361 T6 = _mm_mul_epu32(M0, p->R21.v); in poly1305_blocks()
380 T5 = _mm_mul_epu32(M0, p->R22.v); in poly1305_blocks()
381 T6 = _mm_mul_epu32(M0, p->R23.v); in poly1305_blocks()
400 T5 = _mm_mul_epu32(M0, p->R24.v); in poly1305_blocks()
416 M0 = _mm_and_si128(MMASK, T5); in poly1305_blocks()
423 T0 = _mm_add_epi64(T0, M0); in poly1305_blocks()
478 xmmi M0, M1, M2, M3, M4; in poly1305_combine() local
[all …]
/external/boringssl/src/crypto/bn/asm/
Darmv4-mont.pl268 my ($Bi,$Ni,$M0)=map("d$_",(28..31));
293 vld1.32 {${M0}[0]}, [$n0,:32]
307 vmul.u32 $Ni,$temp,$M0
361 vmul.u32 $Ni,$temp,$M0
486 vmul.u32 $Ni,$temp,$M0
/external/llvm/unittests/Linker/
DLinkModulesTest.cpp289 MDNode *M0 = F->getMetadata("attach"); in TEST_F() local
297 EXPECT_TRUE(M0->isDistinct()); in TEST_F()
318 EXPECT_EQ(M0, F->getMetadata("attach")); in TEST_F()
325 EXPECT_TRUE(M0->isDistinct()); in TEST_F()
/external/llvm/unittests/Analysis/
DScalarEvolutionTest.cpp73 const SCEVMulExpr *M0 = cast<SCEVMulExpr>(P0); in TEST_F() local
77 EXPECT_EQ(cast<SCEVConstant>(M0->getOperand(0))->getValue()->getZExtValue(), in TEST_F()
85 EXPECT_EQ(cast<SCEVUnknown>(M0->getOperand(1))->getValue(), V0); in TEST_F()
94 EXPECT_EQ(cast<SCEVUnknown>(M0->getOperand(1))->getValue(), V0); in TEST_F()
/external/llvm/test/CodeGen/Thumb/
D2012-04-26-M0ISelBug.ll2 ; Cortex-M0 doesn't have 32-bit Thumb2 instructions (except for dmb, mrs, etc.)
/external/opencv/cvaux/src/
Dcvbgfg_codebook.cpp238 uchar m0, m1, m2, M0, M1, M2; in cvBGCodeBookDiff() local
256 m0 = model->modMin[0]; M0 = model->modMax[0]; in cvBGCodeBookDiff()
272 int h0 = p0 - M0, h1 = p1 - M1, h2 = p2 - M2; in cvBGCodeBookDiff()
/external/llvm/test/CodeGen/X86/
Dshuffle-combine-crash.ll5 ; (shuffle (shuffle A, Undef, M0), Undef, M1) -> (shuffle A, Undef, M2)
/external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/
DSIMCCodeEmitter.cpp295 case AMDGPU::M0: return 124; in getRegBinaryCode()
/external/opencv3/modules/calib3d/test/
Dtest_fundam.cpp679 cv::Mat M0 = M, v2_0 = v2; in run_func() local
704 if( M.data != M0.data ) in run_func()
705 M.reshape(M0.channels(), M0.rows).convertTo(M0, M0.type()); in run_func()

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