Searched refs:MSR (Results 1 – 25 of 40) sorted by relevance
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| /external/llvm/test/CodeGen/AArch64/ |
| D | flags-multiuse.ll | 25 ; Currently, the comparison is emitted again. An MSR/MRS pair would also be
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| /external/google-breakpad/src/third_party/libdisasm/ |
| D | TODO | 22 * sysenter, sysexit as CALL types -- preceded by MSR writes
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| /external/llvm/test/MC/ARM/ |
| D | thumbv7m.s | 22 @ MSR
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| D | thumbv7em.s | 10 @ MSR
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| D | thumb2-mclass.s | 38 @ MSR
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| /external/llvm/test/CodeGen/SystemZ/ |
| D | int-mul-02.ll | 7 ; Check MSR.
133 ; Check that multiplications of spilled values can use MS rather than MSR.
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| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb-MSR-MClass.txt | 39 # MSR
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| D | invalid-armv7.txt | 246 # A5.2.11 MSR (immediate), and hints & B6.1.6 MSR (immediate)
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| /external/llvm/test/CodeGen/ARM/ |
| D | copy-cpsr.ll | 26 ; In Thumb mode v7M and v7AR have different MRS/MSR instructions that happen
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrHTM.td | 90 // value of the MSR Transaction State (TS) bits that exist before the
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| /external/selinux/policycoreutils/mcstrans/share/examples/nato/setrans.d/ |
| D | eyes-only.conf | 427 ~c352=MSR # Montserrat
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| D | rel.conf | 433 ~c200,~c352=MSR # Montserrat
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| /external/v8/src/arm64/ |
| D | constants-arm64.h | 661 MSR = SystemSysRegFixed | 0x00000000 enumerator
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| D | disasm-arm64.cc | 1147 case MSR: { in VisitSystem()
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| D | assembler-arm64.cc | 1721 Emit(MSR | Rt(rt) | ImmSystemRegister(sysreg)); in msr()
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| /external/llvm/test/MC/AArch64/ |
| D | arm64-system-encoding.s | 58 ; MSR/MRS instructions
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| /external/regex-re2/benchlog/ |
| D | benchlog.mini | 70 machdep.cpu.features: FPU VME DE PSE TSC MSR PAE MCE CX8 APIC SEP MTRR PGE MCA CMOV PAT PSE36 CLFS…
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| D | benchlog.wreck | 90 machdep.cpu.features: FPU VME DE PSE TSC MSR PAE MCE CX8 APIC SEP MTRR PGE MCA CMOV PAT PSE36 CLFSH…
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| /external/opencv3/doc/ |
| D | opencv.bib | 607 institution = {MSR-TR-2004-92}
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| /external/vixl/src/vixl/a64/ |
| D | constants-a64.h | 688 MSR = SystemSysRegFixed | 0x00000000 enumerator
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| D | disasm-a64.cc | 1306 case MSR: { in VisitSystem()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 2256 return CurDAG->getMachineNode(AArch64::MSR, DL, MVT::Other, in SelectWriteRegister()
2297 return CurDAG->getMachineNode(AArch64::MSR, DL, MVT::Other, in SelectWriteRegister()
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| D | AArch64InstrInfo.cpp | 1812 BuildMI(MBB, I, DL, get(AArch64::MSR)) in copyPhysReg()
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| /external/icu/icu4c/source/data/misc/ |
| D | metadata.txt | 3362 MSR{
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| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrInfo.td | 5204 // No need to have both system and application versions of MSR (immediate) or
5205 // MSR (register), the encodings are the same and the assembly parser has no way
5209 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
5236 // However, the MSR (banked register) system instruction (ARMv7VE) *does* have a
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