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Searched refs:MispredictPenalty (Results 1 – 20 of 20) sorted by relevance

/external/llvm/include/llvm/MC/
DMCSchedule.h184 unsigned MispredictPenalty; member
/external/llvm/lib/Target/PowerPC/
DPPCScheduleA2.td167 let MispredictPenalty = 13;
DPPCScheduleG5.td125 let MispredictPenalty = 16;
DPPCScheduleP7.td389 let MispredictPenalty = 16;
DPPCScheduleP8.td398 let MispredictPenalty = 16;
/external/llvm/lib/Target/ARM/
DARMSubtarget.cpp311 return SchedModel.MispredictPenalty; in getMispredictionPenalty()
DARMScheduleA8.td1072 let MispredictPenalty = 13; // Based on estimate of pipeline depth.
DARMScheduleSwift.td45 let MispredictPenalty = 14; // A branch direction mispredict.
DARMScheduleA9.td1894 let MispredictPenalty = 8; // Based on estimate of pipeline depth.
/external/llvm/lib/Target/X86/
DX86ScheduleSLM.td21 let MispredictPenalty = 10;
DX86SchedSandyBridge.td22 let MispredictPenalty = 16;
DX86ScheduleBtVer2.td23 let MispredictPenalty = 14; // Minimum branch misdirection penalty
DX86SchedHaswell.td21 let MispredictPenalty = 16;
/external/llvm/lib/Target/AArch64/
DAArch64ConditionalCompares.cpp848 unsigned DelayLimit = SchedModel.MispredictPenalty * 3 / 4; in shouldConvert()
DAArch64SchedA53.td26 let MispredictPenalty = 9; // Based on "Cortex-A53 Software Optimisation
DAArch64SchedCyclone.td19 let MispredictPenalty = 16; // 14-19 cycles are typical.
DAArch64SchedA57.td28 let MispredictPenalty = 14; // Fetch + Decode/Rename/Dispatch + Branch
/external/llvm/lib/CodeGen/
DEarlyIfConversion.cpp700 unsigned CritLimit = SchedModel.MispredictPenalty/2; in shouldConvertIf()
/external/llvm/lib/Target/Mips/
DMipsScheduleP5600.td14 int MispredictPenalty = 8; // TODO: Estimated
/external/llvm/include/llvm/Target/
DTargetSchedule.td86 int MispredictPenalty = -1; // Extra cycles for a mispredicted branch.