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Searched refs:NewOpcode (Results 1 – 21 of 21) sorted by relevance

/external/llvm/lib/Target/Hexagon/
DHexagonCFGOptimizer.cpp74 int NewOpcode = 0; in InvertAndChangeJumpTarget() local
77 NewOpcode = Hexagon::J2_jumpf; in InvertAndChangeJumpTarget()
81 NewOpcode = Hexagon::J2_jumpt; in InvertAndChangeJumpTarget()
85 NewOpcode = Hexagon::J2_jumpfnewpt; in InvertAndChangeJumpTarget()
89 NewOpcode = Hexagon::J2_jumptnewpt; in InvertAndChangeJumpTarget()
96 MI->setDesc(TII->get(NewOpcode)); in InvertAndChangeJumpTarget()
DHexagonVLIWPacketizer.cpp416 int NewOpcode; in promoteToDotNew() local
418 NewOpcode = HII->getDotNewPredOp(MI, MBPI); in promoteToDotNew()
420 NewOpcode = HII->getDotNewOp(MI); in promoteToDotNew()
421 MI->setDesc(HII->get(NewOpcode)); in promoteToDotNew()
426 int NewOpcode = HII->getDotOldOp(MI->getOpcode()); in demoteToDotOld() local
427 MI->setDesc(HII->get(NewOpcode)); in demoteToDotOld()
762 int NewOpcode = HII->getDotNewOp(MI); in canPromoteToDotNew() local
763 const MCInstrDesc &D = HII->get(NewOpcode); in canPromoteToDotNew()
DHexagonInstrInfo.cpp1017 unsigned NewOpcode = getInvertedPredicatedOpcode(opcode); in ReverseBranchCondition() local
1018 Cond[0].setImm(NewOpcode); in ReverseBranchCondition()
3135 int NewOpcode = Hexagon::getPredNewOpcode(MI->getOpcode()); in getDotNewPredOp() local
3136 if (NewOpcode >= 0) // Valid predicate new instruction in getDotNewPredOp()
3137 return NewOpcode; in getDotNewPredOp()
3765 unsigned NewOpcode = getInvertedPredicatedOpcode(MI->getOpcode()); in invertAndChangeJumpTarget() local
3774 NewOpcode = reversePrediction(NewOpcode); in invertAndChangeJumpTarget()
3776 MI->setDesc(get(NewOpcode)); in invertAndChangeJumpTarget()
/external/llvm/lib/Target/XCore/
DXCoreRegisterInfo.cpp138 int NewOpcode; in InsertSPImmInst() local
140 NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6; in InsertSPImmInst()
141 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) in InsertSPImmInst()
146 NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6; in InsertSPImmInst()
147 BuildMI(MBB, II, dl, TII.get(NewOpcode)) in InsertSPImmInst()
153 NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6; in InsertSPImmInst()
154 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) in InsertSPImmInst()
/external/llvm/lib/Target/AMDGPU/
DAMDILCFGStructurizer.cpp231 void insertInstrEnd(MachineBasicBlock *MBB, int NewOpcode,
233 MachineInstr *insertInstrBefore(MachineBasicBlock *MBB, int NewOpcode,
235 MachineInstr *insertInstrBefore(MachineBasicBlock::iterator I, int NewOpcode);
236 void insertCondBranchBefore(MachineBasicBlock::iterator I, int NewOpcode,
239 MachineBasicBlock::iterator I, int NewOpcode, int RegNum,
241 void insertCondBranchEnd(MachineBasicBlock *MBB, int NewOpcode, int RegNum);
472 int NewOpcode, DebugLoc DL) { in insertInstrEnd() argument
474 ->CreateMachineInstr(TII->get(NewOpcode), DL); in insertInstrEnd()
481 int NewOpcode, DebugLoc DL) { in insertInstrBefore() argument
483 MBB->getParent()->CreateMachineInstr(TII->get(NewOpcode), DL); in insertInstrBefore()
[all …]
DSIInstrInfo.cpp2348 unsigned NewOpcode = getVALUOp(*MI); in moveSMRDToVALU() local
2400 const MCInstrDesc &NewInstDesc = get(NewOpcode); in moveSMRDToVALU()
2455 unsigned NewOpcode = getVALUOp(*Inst); in moveToVALU() local
2498 NewOpcode = AMDGPU::V_LSHLREV_B32_e64; in moveToVALU()
2504 NewOpcode = AMDGPU::V_ASHRREV_I32_e64; in moveToVALU()
2510 NewOpcode = AMDGPU::V_LSHRREV_B32_e64; in moveToVALU()
2516 NewOpcode = AMDGPU::V_LSHLREV_B64; in moveToVALU()
2522 NewOpcode = AMDGPU::V_ASHRREV_I64; in moveToVALU()
2528 NewOpcode = AMDGPU::V_LSHRREV_B64; in moveToVALU()
2543 if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END) { in moveToVALU()
[all …]
DSIISelLowering.cpp2356 unsigned NewOpcode = TII->getMaskedMIMGOp(MI->getOpcode(), BitsSet); in AdjustInstrPostInstrSelection() local
2357 MI->setDesc(TII->get(NewOpcode)); in AdjustInstrPostInstrSelection()
/external/llvm/lib/Target/X86/
DX86FixupLEAs.cpp264 int NewOpcode; in fixupIncDec() local
268 NewOpcode = isINC ? X86::INC16r : X86::DEC16r; in fixupIncDec()
272 NewOpcode = isINC ? X86::INC32r : X86::DEC32r; in fixupIncDec()
275 NewOpcode = isINC ? X86::INC64r : X86::DEC64r; in fixupIncDec()
280 BuildMI(*MFI, I, MI->getDebugLoc(), TII->get(NewOpcode)) in fixupIncDec()
DX86MCInstLower.cpp322 unsigned NewOpcode = 0; in SimplifyMOVSX() local
329 NewOpcode = X86::CBW; in SimplifyMOVSX()
333 NewOpcode = X86::CWDE; in SimplifyMOVSX()
337 NewOpcode = X86::CDQE; in SimplifyMOVSX()
341 if (NewOpcode != 0) { in SimplifyMOVSX()
343 Inst.setOpcode(NewOpcode); in SimplifyMOVSX()
DX86InstrInfo.cpp4924 unsigned NewOpcode = 0; in optimizeCompareInstr() local
4947 case X86::SUB64rm: NewOpcode = X86::CMP64rm; break; in optimizeCompareInstr()
4948 case X86::SUB32rm: NewOpcode = X86::CMP32rm; break; in optimizeCompareInstr()
4949 case X86::SUB16rm: NewOpcode = X86::CMP16rm; break; in optimizeCompareInstr()
4950 case X86::SUB8rm: NewOpcode = X86::CMP8rm; break; in optimizeCompareInstr()
4951 case X86::SUB64rr: NewOpcode = X86::CMP64rr; break; in optimizeCompareInstr()
4952 case X86::SUB32rr: NewOpcode = X86::CMP32rr; break; in optimizeCompareInstr()
4953 case X86::SUB16rr: NewOpcode = X86::CMP16rr; break; in optimizeCompareInstr()
4954 case X86::SUB8rr: NewOpcode = X86::CMP8rr; break; in optimizeCompareInstr()
4955 case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break; in optimizeCompareInstr()
[all …]
/external/llvm/lib/Target/Mips/MCTargetDesc/
DMipsMCCodeEmitter.cpp183 int NewOpcode = -1; in encodeInstruction() local
186 NewOpcode = Mips::MipsR62MicroMipsR6(Opcode, Mips::Arch_micromipsr6); in encodeInstruction()
187 if (NewOpcode == -1) in encodeInstruction()
188 NewOpcode = Mips::Std2MicroMipsR6(Opcode, Mips::Arch_micromipsr6); in encodeInstruction()
191 NewOpcode = Mips::Std2MicroMips(Opcode, Mips::Arch_micromips); in encodeInstruction()
194 if (NewOpcode == -1) in encodeInstruction()
195 NewOpcode = Mips::Dsp2MicroMips(Opcode, Mips::Arch_mmdsp); in encodeInstruction()
197 if (NewOpcode != -1) { in encodeInstruction()
201 Opcode = NewOpcode; in encodeInstruction()
202 TmpInst.setOpcode (NewOpcode); in encodeInstruction()
/external/llvm/lib/Target/SystemZ/
DSystemZFrameLowering.cpp438 unsigned NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset); in emitEpilogue() local
442 if (!NewOpcode) { in emitEpilogue()
447 NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset); in emitEpilogue()
448 assert(NewOpcode && "No restore instruction available"); in emitEpilogue()
451 MBBI->setDesc(ZII->get(NewOpcode)); in emitEpilogue()
DSystemZInstrInfo.cpp51 unsigned NewOpcode) const { in splitMove()
78 unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm()); in splitMove()
79 unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm()); in splitMove()
96 unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset); in splitAdjDynAlloc() local
97 assert(NewOpcode && "No support for huge argument lists yet"); in splitAdjDynAlloc()
98 MI->setDesc(get(NewOpcode)); in splitAdjDynAlloc()
731 unsigned NewOpcode; in convertToThreeAddress() local
733 NewOpcode = SystemZ::RISBG; in convertToThreeAddress()
736 NewOpcode = SystemZ::RISBGN; in convertToThreeAddress()
738 NewOpcode = SystemZ::RISBMux; in convertToThreeAddress()
[all …]
DSystemZInstrInfo.h121 void splitMove(MachineBasicBlock::iterator MI, unsigned NewOpcode) const;
/external/llvm/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp4118 unsigned NewOpcode; in PeepholePPC64ZExt() local
4122 case PPC::RLWINM: NewOpcode = PPC::RLWINM8; break; in PeepholePPC64ZExt()
4123 case PPC::RLWNM: NewOpcode = PPC::RLWNM8; break; in PeepholePPC64ZExt()
4124 case PPC::SLW: NewOpcode = PPC::SLW8; break; in PeepholePPC64ZExt()
4125 case PPC::SRW: NewOpcode = PPC::SRW8; break; in PeepholePPC64ZExt()
4126 case PPC::LI: NewOpcode = PPC::LI8; break; in PeepholePPC64ZExt()
4127 case PPC::LIS: NewOpcode = PPC::LIS8; break; in PeepholePPC64ZExt()
4128 case PPC::LHBRX: NewOpcode = PPC::LHBRX8; break; in PeepholePPC64ZExt()
4129 case PPC::LWBRX: NewOpcode = PPC::LWBRX8; break; in PeepholePPC64ZExt()
4130 case PPC::CNTLZW: NewOpcode = PPC::CNTLZW8; break; in PeepholePPC64ZExt()
[all …]
DPPCAsmPrinter.cpp980 unsigned NewOpcode = in EmitInstruction() local
984 EmitToStreamer(*OutStreamer, MCInstBuilder(NewOpcode) in EmitInstruction()
994 unsigned NewOpcode = in EmitInstruction() local
1000 EmitToStreamer(*OutStreamer, MCInstBuilder(NewOpcode) in EmitInstruction()
DPPCRegisterInfo.cpp881 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; in eliminateFrameIndex() local
882 MI.setDesc(TII.get(NewOpcode)); in eliminateFrameIndex()
/external/llvm/lib/Target/PowerPC/AsmParser/
DPPCAsmParser.cpp1634 std::string NewOpcode; in ParseInstruction() local
1637 NewOpcode = Name; in ParseInstruction()
1638 NewOpcode += '+'; in ParseInstruction()
1639 Name = NewOpcode; in ParseInstruction()
1643 NewOpcode = Name; in ParseInstruction()
1644 NewOpcode += '-'; in ParseInstruction()
1645 Name = NewOpcode; in ParseInstruction()
1651 if (!NewOpcode.empty()) // Underlying memory for Name is volatile. in ParseInstruction()
1659 if (!NewOpcode.empty()) // Underlying memory for Name is volatile. in ParseInstruction()
/external/llvm/lib/Target/Mips/
DMipsDelaySlotFiller.cpp513 unsigned NewOpcode = in replaceWithCompactBranch() local
517 const MCInstrDesc &NewDesc = TII->get(NewOpcode); in replaceWithCompactBranch()
/external/llvm/lib/Target/Mips/AsmParser/
DMipsAsmParser.cpp2633 unsigned NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM32_MM : Mips::LWM32_MM; in expandLoadStoreMultiple() local
2647 NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM16_MMR6 : Mips::LWM16_MMR6; in expandLoadStoreMultiple()
2649 NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM16_MM : Mips::LWM16_MM; in expandLoadStoreMultiple()
2652 Inst.setOpcode(NewOpcode); in expandLoadStoreMultiple()
/external/llvm/lib/CodeGen/SelectionDAG/
DDAGCombiner.cpp4158 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; in visitXOR() local
4162 return DAG.getNode(NewOpcode, SDLoc(N), VT, LHS, RHS); in visitXOR()
4170 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; in visitXOR() local
4174 return DAG.getNode(NewOpcode, SDLoc(N), VT, LHS, RHS); in visitXOR()