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Searched refs:Op2 (Results 1 – 25 of 69) sorted by relevance

123

/external/llvm/lib/Target/XCore/Disassembler/
DXCoreDisassembler.cpp241 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) { in Decode2OpInstruction() argument
254 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2); in Decode2OpInstruction()
259 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2, in Decode3OpInstruction() argument
269 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2); in Decode3OpInstruction()
347 unsigned Op1, Op2; in Decode2RInstruction() local
348 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); in Decode2RInstruction()
353 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); in Decode2RInstruction()
360 unsigned Op1, Op2; in Decode2RImmInstruction() local
361 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); in Decode2RImmInstruction()
366 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); in Decode2RImmInstruction()
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/external/llvm/include/llvm/Target/
DTargetSelectionDAGInfo.h51 SDValue Op1, SDValue Op2, in EmitTargetCodeForMemcpy() argument
68 SDValue Op1, SDValue Op2, in EmitTargetCodeForMemmove() argument
84 SDValue Op1, SDValue Op2, in EmitTargetCodeForMemset() argument
97 SDValue Op1, SDValue Op2, in EmitTargetCodeForMemcmp() argument
136 SDValue Op1, SDValue Op2, in EmitTargetCodeForStrcmp() argument
/external/llvm/lib/Target/X86/
DX86OptimizeLEAs.cpp206 const MachineOperand *Op2 = &MI2.getOperand(N2 + X86::AddrDisp); in isSimilarMemOp() local
207 if (!isIdenticalOp(*Op1, *Op2)) { in isSimilarMemOp()
208 if (Op1->isImm() && Op2->isImm()) in isSimilarMemOp()
209 AddrDispShift = Op1->getImm() - Op2->getImm(); in isSimilarMemOp()
210 else if (Op1->isGlobal() && Op2->isGlobal() && in isSimilarMemOp()
211 Op1->getGlobal() == Op2->getGlobal()) in isSimilarMemOp()
212 AddrDispShift = Op1->getOffset() - Op2->getOffset(); in isSimilarMemOp()
/external/llvm/lib/Target/Hexagon/
DHexagonExpandPredSpillCode.cpp103 MachineOperand &Op2 = MI->getOperand(2); in runOnMachineFunction() local
119 NewMI->addOperand(Op2); in runOnMachineFunction()
146 MachineOperand &Op2 = MI->getOperand(2); in runOnMachineFunction() local
157 NewMI->addOperand(Op2); in runOnMachineFunction()
188 MachineOperand &Op2 = MI->getOperand(2); in runOnMachineFunction() local
198 NewMI->addOperand(Op2); in runOnMachineFunction()
225 MachineOperand &Op2 = MI->getOperand(2); in runOnMachineFunction() local
239 NewMI->addOperand(Op2); in runOnMachineFunction()
DHexagonSplitDouble.cpp701 MachineOperand &Op2 = MI->getOperand(2); in splitCombine() local
719 if (Op2.isImm()) { in splitCombine()
721 .addImm(Op2.getImm()); in splitCombine()
722 } else if (Op2.isReg()) { in splitCombine()
724 .addReg(Op2.getReg(), getRegState(Op2), Op2.getSubReg()); in splitCombine()
755 MachineOperand &Op2 = MI->getOperand(2); in splitShift() local
756 assert(Op0.isReg() && Op1.isReg() && Op2.isImm()); in splitShift()
757 int64_t Sh64 = Op2.getImm(); in splitShift()
879 MachineOperand &Op2 = MI->getOperand(2); in splitAslOr() local
881 assert(Op0.isReg() && Op1.isReg() && Op2.isReg() && Op3.isImm()); in splitAslOr()
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DHexagonPeephole.cpp291 MachineOperand Op2 = MI->getOperand(S2); in runOnMachineFunction() local
292 ChangeOpInto(MI->getOperand(S1), Op2); in runOnMachineFunction()
/external/llvm/include/llvm/CodeGen/
DSelectionDAG.h647 SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2,
653 Ops.push_back(Op2);
918 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2);
919 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2,
921 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2,
923 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2,
934 SDValue Op1, SDValue Op2);
936 SDValue Op1, SDValue Op2, SDValue Op3);
949 EVT VT2, SDValue Op1, SDValue Op2);
951 EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
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DISDOpcodes.h911 CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, bool isInteger);
917 CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, bool isInteger);
/external/llvm/lib/Target/AArch64/InstPrinter/
DAArch64InstPrinter.cpp68 const MCOperand &Op2 = MI->getOperand(2); in printInst() local
73 if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) { in printInst()
109 if (Op2.isImm() && Op3.isImm()) { in printInst()
112 int64_t immr = Op2.getImm(); in printInst()
143 if (Op2.getImm() > Op3.getImm()) { in printInst()
146 << ", #" << (Is64Bit ? 64 : 32) - Op2.getImm() << ", #" << Op3.getImm() + 1; in printInst()
154 << ", #" << Op2.getImm() << ", #" << Op3.getImm() - Op2.getImm() + 1; in printInst()
161 const MCOperand &Op2 = MI->getOperand(2); in printInst() local
165 if ((Op2.getReg() == AArch64::WZR || Op2.getReg() == AArch64::XZR) && in printInst()
183 << getRegisterName(Op2.getReg()) << ", #" << LSB << ", #" << Width; in printInst()
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/external/llvm/lib/Target/BPF/MCTargetDesc/
DBPFMCCodeEmitter.cpp161 MCOperand Op2 = MI.getOperand(2); in getMemoryOpValue() local
162 assert(Op2.isImm() && "Second operand is not immediate."); in getMemoryOpValue()
163 Encoding |= Op2.getImm() & 0xffff; in getMemoryOpValue()
/external/opencv3/modules/cudev/include/opencv2/cudev/warp/detail/
Dreduce.hpp157 …class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8,…
162 … const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op) in merge() argument
178 …class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8,…
182 … const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op) in mergeShfl() argument
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp736 SDValue Op2 = Op.getOperand(2); in ExpandSELECT() local
739 && Op1.getValueType() == Op2.getValueType() && "Invalid type"); in ExpandSELECT()
773 Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2); in ExpandSELECT()
780 Op2 = DAG.getNode(ISD::AND, DL, MaskTy, Op2, NotMask); in ExpandSELECT()
781 SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2); in ExpandSELECT()
933 SDValue Op2 = Op.getOperand(2); in ExpandVSELECT() local
961 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2); in ExpandVSELECT()
968 Op2 = DAG.getNode(ISD::AND, DL, VT, Op2, NotMask); in ExpandVSELECT()
969 SDValue Val = DAG.getNode(ISD::OR, DL, VT, Op1, Op2); in ExpandVSELECT()
/external/llvm/lib/Target/X86/AsmParser/
DX86AsmParser.cpp178 ICToken Op2 = OperandStack.pop_back_val(); in execute() local
185 Val = Op1.second + Op2.second; in execute()
189 Val = Op1.second - Op2.second; in execute()
193 assert (Op1.first == IC_IMM && Op2.first == IC_IMM && in execute()
195 Val = Op1.second * Op2.second; in execute()
199 assert (Op1.first == IC_IMM && Op2.first == IC_IMM && in execute()
201 assert (Op2.second != 0 && "Division by zero!"); in execute()
202 Val = Op1.second / Op2.second; in execute()
206 assert (Op1.first == IC_IMM && Op2.first == IC_IMM && in execute()
208 Val = Op1.second | Op2.second; in execute()
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/external/opencv3/modules/cudev/include/opencv2/cudev/block/
Dreduce.hpp71 …class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8,…
75 … const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op) in blockReduce() argument
80 const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>&>(smem, val, tid, op); in blockReduce()
/external/llvm/lib/Analysis/
DConstantFolding.cpp1654 if (ConstantFP *Op2 = dyn_cast<ConstantFP>(Operands[1])) { in ConstantFoldScalarCall() local
1655 if (Op2->getType() != Op1->getType()) in ConstantFoldScalarCall()
1658 double Op2V = getValueAsDouble(Op2); in ConstantFoldScalarCall()
1664 APFloat V2 = Op2->getValueAPF(); in ConstantFoldScalarCall()
1671 const APFloat &C2 = Op2->getValueAPF(); in ConstantFoldScalarCall()
1677 const APFloat &C2 = Op2->getValueAPF(); in ConstantFoldScalarCall()
1710 if (ConstantInt *Op2 = dyn_cast<ConstantInt>(Operands[1])) { in ConstantFoldScalarCall() local
1724 Res = Op1->getValue().sadd_ov(Op2->getValue(), Overflow); in ConstantFoldScalarCall()
1727 Res = Op1->getValue().uadd_ov(Op2->getValue(), Overflow); in ConstantFoldScalarCall()
1730 Res = Op1->getValue().ssub_ov(Op2->getValue(), Overflow); in ConstantFoldScalarCall()
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/external/llvm/lib/Target/AArch64/Utils/
DAArch64BaseInfo.cpp867 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; in fromString() local
873 Ops[5].getAsInteger(10, Op2); in fromString()
874 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2; in fromString()
903 uint32_t Op2 = Bits & 0x7; in toString() local
906 + "_c" + utostr(CRm) + "_" + utostr(Op2); in toString()
/external/llvm/lib/Target/XCore/
DXCoreSelectionDAGInfo.h29 SDValue Op1, SDValue Op2,
/external/opencv3/modules/core/include/opencv2/core/cuda/detail/
Dreduce.hpp168 …class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8,…
173 … const thrust::tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op) in merge() argument
178 …class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8,…
182 … const thrust::tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op) in mergeShfl() argument
/external/llvm/lib/Transforms/Scalar/
DNaryReassociate.cpp160 bool matchTernaryOp(BinaryOperator *I, Value *V, Value *&Op1, Value *&Op2);
529 Value *&Op2) { in matchTernaryOp() argument
532 return match(V, m_Add(m_Value(Op1), m_Value(Op2))); in matchTernaryOp()
534 return match(V, m_Mul(m_Value(Op1), m_Value(Op2))); in matchTernaryOp()
DLoopRerollPass.cpp1190 Value *Op2 = RootInst->getOperand(j); in validate() local
1196 if (Instruction *Op2I = dyn_cast<Instruction>(Op2)) in validate()
1200 DenseMap<Value *, Value *>::iterator BMI = BaseMap.find(Op2); in validate()
1202 Op2 = BMI->second; in validate()
1205 if (DRS.Roots[Iter-1] == (Instruction*) Op2) { in validate()
1206 Op2 = DRS.BaseInst; in validate()
1212 if (BaseInst->getOperand(Swapped ? unsigned(!j) : j) != Op2) { in validate()
1219 BaseInst->getOperand(!j) == Op2) { in validate()
/external/opencv3/modules/cudev/include/opencv2/cudev/block/detail/
Dreduce.hpp186 …class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8,…
191 … const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op) in merge() argument
207 …class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8,…
211 … const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op) in mergeShfl() argument
/external/opencv3/modules/cudaarithm/src/cuda/
Dminmax_mat.cu86 template <class Op2>
95 gridTransformBinary(src1_, src2_, dst_, Op2(), stream); in minMaxMat_v2()
/external/opencv3/modules/cudev/include/opencv2/cudev/warp/
Dreduce.hpp69 …class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8,…
73 … const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op) in warpReduce() argument
78 const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>&>(smem, val, tid, op); in warpReduce()
/external/llvm/lib/Target/ARM/
DARMSelectionDAGInfo.h59 SDValue Op1, SDValue Op2,
/external/opencv3/modules/core/include/opencv2/core/cuda/
Dreduce.hpp66 …class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8,…
70 … const thrust::tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op) in reduce() argument
75 … const thrust::tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>&>(smem, val, tid, op); in reduce()

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