| /external/llvm/lib/Target/PowerPC/ |
| D | PPCTLSDynamicCall.cpp | 75 unsigned Opc1, Opc2; in processBlock() local
85 Opc1 = PPC::ADDItlsgdL; in processBlock()
89 Opc1 = PPC::ADDItlsldL; in processBlock()
93 Opc1 = PPC::ADDItlsgdL32; in processBlock()
97 Opc1 = PPC::ADDItlsldL32; in processBlock()
103 MachineInstr *Addi = BuildMI(MBB, I, DL, TII->get(Opc1), GPR3) in processBlock()
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| D | PPCISelDAGToDAG.cpp | 3012 unsigned Opc1, Opc2, Opc3; in Select() local
3016 Opc1 = PPC::VSPLTISB; in Select()
3021 Opc1 = PPC::VSPLTISH; in Select()
3027 Opc1 = PPC::VSPLTISW; in Select()
3041 SDNode *Tmp = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); in Select()
3053 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); in Select()
3055 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); in Select()
3067 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); in Select()
3069 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); in Select()
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| /external/llvm/lib/Target/Mips/ |
| D | Mips16ISelLowering.h | 56 MachineBasicBlock *emitSeliT16(unsigned Opc1, unsigned Opc2,
60 MachineBasicBlock *emitSelT16(unsigned Opc1, unsigned Opc2,
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| D | Mips16ISelLowering.cpp | 583 Mips16TargetLowering::emitSelT16(unsigned Opc1, unsigned Opc2, MachineInstr *MI, in emitSelT16() argument
620 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB); in emitSelT16()
646 Mips16TargetLowering::emitSeliT16(unsigned Opc1, unsigned Opc2, in emitSeliT16() argument
684 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB); in emitSeliT16()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 54 unsigned Opc1 = N1->getMachineOpcode(); in nodesHaveSameOperandValue() local
57 int Op1Idx = AMDGPU::getNamedOperandIdx(Opc1, OpName); in nodesHaveSameOperandValue()
99 unsigned Opc1 = Load1->getMachineOpcode(); in areLoadsFromSameBasePtr() local
102 if (!get(Opc0).mayLoad() || !get(Opc1).mayLoad()) in areLoadsFromSameBasePtr()
105 if (isDS(Opc0) && isDS(Opc1)) { in areLoadsFromSameBasePtr()
123 AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::data1) != -1) in areLoadsFromSameBasePtr()
131 if (isSMRD(Opc0) && isSMRD(Opc1)) { in areLoadsFromSameBasePtr()
156 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1))) { in areLoadsFromSameBasePtr()
166 int OffIdx1 = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset); in areLoadsFromSameBasePtr()
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| /external/llvm/include/llvm/IR/ |
| D | PatternMatch.h | 635 template <typename LHS_t, typename RHS_t, unsigned Opc1, unsigned Opc2>
643 if (V->getValueID() == Value::InstructionVal + Opc1 || in match()
649 return (CE->getOpcode() == Opc1 || CE->getOpcode() == Opc2) && in match()
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrInfo.cpp | 6414 unsigned Opc1 = Load1->getMachineOpcode(); in areLoadsFromSameBasePtr() local
6416 switch (Opc1) { in areLoadsFromSameBasePtr()
6522 unsigned Opc1 = Load1->getMachineOpcode(); in shouldScheduleLoadsNear() local
6524 if (Opc1 != Opc2) in shouldScheduleLoadsNear()
6527 switch (Opc1) { in shouldScheduleLoadsNear()
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| D | X86ISelLowering.cpp | 16312 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1; in LowerINTRINSIC_WO_CHAIN()
16330 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1; in LowerINTRINSIC_WO_CHAIN()
16362 unsigned Opc = IntrData->Opc1 ? IntrData->Opc1 : IntrData->Opc0; in LowerINTRINSIC_WO_CHAIN()
16387 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1; in LowerINTRINSIC_WO_CHAIN()
16473 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1; in LowerINTRINSIC_WO_CHAIN()
16531 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1; in LowerINTRINSIC_WO_CHAIN()
16613 if (IntrData->Opc1 != 0) { in LowerINTRINSIC_WO_CHAIN()
16617 Cmp = DAG.getNode(IntrData->Opc1, dl, MaskVT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
16646 if (IntrData->Opc1 != 0) { in LowerINTRINSIC_WO_CHAIN()
16650 Cmp = DAG.getNode(IntrData->Opc1, dl, MVT::i1, Src1, Src2, CC, Rnd); in LowerINTRINSIC_WO_CHAIN()
[all …]
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| D | X86IntrinsicsInfo.h | 41 unsigned Opc1; member
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 376 unsigned Opc1 = Is64Bit ? AArch64::MOVi64imm : AArch64::MOVi32imm; in materializeFP() local
381 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc1), TmpReg) in materializeFP()
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