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Searched refs:OperandIndex (Results 1 – 5 of 5) sorted by relevance

/external/llvm/include/llvm/CodeGen/
DScheduleDAGInstrs.h48 unsigned OperandIndex; member
51 unsigned OperandIndex, SUnit *SU) in VReg2SUnitOperIdx()
52 : VReg2SUnit(VReg, LaneMask, SU), OperandIndex(OperandIndex) {} in VReg2SUnitOperIdx()
/external/llvm/utils/TableGen/
DX86DisassemblerTables.cpp637 for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS; in emitInstructionInfo() local
638 ++OperandIndex) { in emitInstructionInfo()
640 .operands[OperandIndex].encoding; in emitInstructionInfo()
642 .operands[OperandIndex].type; in emitInstructionInfo()
670 for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS; in emitInstructionInfo() local
671 ++OperandIndex) { in emitInstructionInfo()
673 .operands[OperandIndex].encoding; in emitInstructionInfo()
675 .operands[OperandIndex].type; in emitInstructionInfo()
/external/llvm/lib/Target/X86/InstPrinter/
DX86InstComments.cpp39 unsigned OperandIndex) { in getRegOperandVectorVT() argument
40 unsigned OpReg = MI->getOperand(OperandIndex).getReg(); in getRegOperandVectorVT()
/external/clang/lib/CodeGen/
DTargetInfo.cpp977 unsigned OperandIndex; in rewriteInputConstraintReferences() local
978 if (!OperandStr.getAsInteger(10, OperandIndex)) { in rewriteInputConstraintReferences()
979 if (OperandIndex >= FirstIn) in rewriteInputConstraintReferences()
980 OperandIndex += NumNewOuts; in rewriteInputConstraintReferences()
981 OS << OperandIndex; in rewriteInputConstraintReferences()
/external/llvm/lib/CodeGen/
DScheduleDAGInstrs.cpp427 I->OperandIndex)); in addVRegDefDeps()