Home
last modified time | relevance | path

Searched refs:PPC (Results 1 – 25 of 159) sorted by relevance

1234567

/external/llvm/lib/Target/PowerPC/Disassembler/
DPPCDisassembler.cpp66 PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
67 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
71 PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
72 PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
73 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
74 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
75 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
76 PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
77 PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
78 PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
[all …]
/external/llvm/lib/Target/PowerPC/MCTargetDesc/
DPPCPredicates.cpp19 PPC::Predicate PPC::InvertPredicate(PPC::Predicate Opcode) { in InvertPredicate()
21 case PPC::PRED_EQ: return PPC::PRED_NE; in InvertPredicate()
22 case PPC::PRED_NE: return PPC::PRED_EQ; in InvertPredicate()
23 case PPC::PRED_LT: return PPC::PRED_GE; in InvertPredicate()
24 case PPC::PRED_GE: return PPC::PRED_LT; in InvertPredicate()
25 case PPC::PRED_GT: return PPC::PRED_LE; in InvertPredicate()
26 case PPC::PRED_LE: return PPC::PRED_GT; in InvertPredicate()
27 case PPC::PRED_NU: return PPC::PRED_UN; in InvertPredicate()
28 case PPC::PRED_UN: return PPC::PRED_NU; in InvertPredicate()
29 case PPC::PRED_EQ_MINUS: return PPC::PRED_NE_PLUS; in InvertPredicate()
[all …]
DPPCAsmBackend.cpp35 case PPC::fixup_ppc_nofixup: in adjustFixupValue()
37 case PPC::fixup_ppc_brcond14: in adjustFixupValue()
38 case PPC::fixup_ppc_brcond14abs: in adjustFixupValue()
40 case PPC::fixup_ppc_br24: in adjustFixupValue()
41 case PPC::fixup_ppc_br24abs: in adjustFixupValue()
43 case PPC::fixup_ppc_half16: in adjustFixupValue()
45 case PPC::fixup_ppc_half16ds: in adjustFixupValue()
57 case PPC::fixup_ppc_half16: in getFixupKindNumBytes()
58 case PPC::fixup_ppc_half16ds: in getFixupKindNumBytes()
61 case PPC::fixup_ppc_brcond14: in getFixupKindNumBytes()
[all …]
DPPCMCCodeEmitter.cpp161 (MCFixupKind)PPC::fixup_ppc_br24)); in getDirectBrEncoding()
173 (MCFixupKind)PPC::fixup_ppc_brcond14)); in getCondBrEncoding()
186 (MCFixupKind)PPC::fixup_ppc_br24abs)); in getAbsDirectBrEncoding()
199 (MCFixupKind)PPC::fixup_ppc_brcond14abs)); in getAbsCondBrEncoding()
211 (MCFixupKind)PPC::fixup_ppc_half16)); in getImm16Encoding()
229 (MCFixupKind)PPC::fixup_ppc_half16)); in getMemRIEncoding()
248 (MCFixupKind)PPC::fixup_ppc_half16ds)); in getMemRIXEncoding()
311 (MCFixupKind)PPC::fixup_ppc_nofixup)); in getTLSRegEncoding()
314 return CTX.getRegisterInfo()->getEncodingValue(isPPC64 ? PPC::X13 : PPC::R2); in getTLSRegEncoding()
325 (MCFixupKind)PPC::fixup_ppc_nofixup)); in getTLSCallEncoding()
[all …]
/external/llvm/lib/Target/PowerPC/AsmParser/
DPPCAsmParser.cpp37 PPC::R0, PPC::R1, PPC::R2, PPC::R3,
38 PPC::R4, PPC::R5, PPC::R6, PPC::R7,
39 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
40 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
41 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
42 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
43 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
44 PPC::R28, PPC::R29, PPC::R30, PPC::R31
47 PPC::ZERO,
48 PPC::R1, PPC::R2, PPC::R3,
[all …]
/external/llvm/lib/Target/PowerPC/
DPPCInstrInfo.cpp68 : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP), in PPCInstrInfo()
78 if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 || in CreateTargetHazardRecognizer()
79 Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) { in CreateTargetHazardRecognizer()
96 if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8) in CreateTargetPostRAHazardRecognizer()
100 if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 && in CreateTargetPostRAHazardRecognizer()
101 Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) { in CreateTargetPostRAHazardRecognizer()
157 IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) || in getOperandLatency()
158 MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass); in getOperandLatency()
160 IsRegCR = PPC::CRRCRegClass.contains(Reg) || in getOperandLatency()
161 PPC::CRBITRCRegClass.contains(Reg); in getOperandLatency()
[all …]
DPPCRegisterInfo.cpp61 : PPCGenRegisterInfo(TM.isPPC64() ? PPC::LR8 : PPC::LR, in PPCRegisterInfo()
65 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; in PPCRegisterInfo()
66 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; in PPCRegisterInfo()
67 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; in PPCRegisterInfo()
68 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; in PPCRegisterInfo()
69 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; in PPCRegisterInfo()
70 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; in PPCRegisterInfo()
71 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; in PPCRegisterInfo()
72 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; in PPCRegisterInfo()
73 ImmToIdxMap[PPC::LWA_32] = PPC::LWAX_32; in PPCRegisterInfo()
[all …]
DPPCFrameLowering.cpp34 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
35 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
36 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
37 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
99 static const SpillSlot darwin64Offsets = {PPC::X31, -8}; in getCalleeSavedSpillSlots()
102 static const SpillSlot darwinOffsets = {PPC::R31, -4}; in getCalleeSavedSpillSlots()
118 {PPC::F31, -8}, in getCalleeSavedSpillSlots()
119 {PPC::F30, -16}, in getCalleeSavedSpillSlots()
120 {PPC::F29, -24}, in getCalleeSavedSpillSlots()
121 {PPC::F28, -32}, in getCalleeSavedSpillSlots()
[all …]
DPPCRegisterInfo.h28 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT || in getCRFromCRBit()
29 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN) in getCRFromCRBit()
30 Reg = PPC::CR0; in getCRFromCRBit()
31 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT || in getCRFromCRBit()
32 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN) in getCRFromCRBit()
33 Reg = PPC::CR1; in getCRFromCRBit()
34 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT || in getCRFromCRBit()
35 SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN) in getCRFromCRBit()
36 Reg = PPC::CR2; in getCRFromCRBit()
37 else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT || in getCRFromCRBit()
[all …]
DPPCVSXSwapRemoval.cpp174 return (isRegInClass(Reg, &PPC::VSRCRegClass) || in isVecReg()
175 isRegInClass(Reg, &PPC::VRRCRegClass)); in isVecReg()
180 return (isRegInClass(Reg, &PPC::VSFRCRegClass) || in isScalarVecReg()
181 isRegInClass(Reg, &PPC::VSSRCRegClass)); in isScalarVecReg()
288 case PPC::XXPERMDI: { in gatherVectorInstructions()
337 case PPC::LVX: in gatherVectorInstructions()
344 case PPC::LXVD2X: in gatherVectorInstructions()
345 case PPC::LXVW4X: in gatherVectorInstructions()
351 case PPC::LXSDX: in gatherVectorInstructions()
352 case PPC::LXSSPX: in gatherVectorInstructions()
[all …]
DPPCFastISel.cpp149 return MRI.getRegClass(Register)->getID() == PPC::VSFRCRegClassID; in isVSFRCRegister()
152 return MRI.getRegClass(Register)->getID() == PPC::VSSRCRegClassID; in isVSSRCRegister()
158 unsigned FP64LoadOpc = PPC::LFD);
212 static Optional<PPC::Predicate> getComparePred(CmpInst::Predicate Pred) { in getComparePred()
224 return Optional<PPC::Predicate>(); in getComparePred()
228 return PPC::PRED_EQ; in getComparePred()
233 return PPC::PRED_GT; in getComparePred()
238 return PPC::PRED_GE; in getComparePred()
243 return PPC::PRED_LT; in getComparePred()
248 return PPC::PRED_LE; in getComparePred()
[all …]
DPPCISelDAGToDAG.cpp259 if (RegInfo->getRegClass(Reg) == &PPC::VRRCRegClass) { in InsertVRSaveCode()
278 unsigned InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass); in InsertVRSaveCode()
279 unsigned UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass); in InsertVRSaveCode()
289 BuildMI(EntryBB, IP, dl, TII.get(PPC::MFVRSAVE), InVRSAVE); in InsertVRSaveCode()
290 BuildMI(EntryBB, IP, dl, TII.get(PPC::UPDATE_VRSAVE), in InsertVRSaveCode()
292 BuildMI(EntryBB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE); in InsertVRSaveCode()
306 BuildMI(*BB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE); in InsertVRSaveCode()
326 GlobalBaseReg = PPC::R30; in getGlobalBaseReg()
328 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MoveGOTtoLR)); in getGlobalBaseReg()
329 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg); in getGlobalBaseReg()
[all …]
DPPCAsmPrinter.cpp343 MII->getOpcode() == PPC::DBG_VALUE || in LowerSTACKMAP()
353 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::NOP)); in LowerSTACKMAP()
374 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::LI8) in LowerPATCHPOINT()
378 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::RLDIC) in LowerPATCHPOINT()
383 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::ORIS8) in LowerPATCHPOINT()
388 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::ORI8) in LowerPATCHPOINT()
395 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::STD) in LowerPATCHPOINT()
396 .addReg(PPC::X2) in LowerPATCHPOINT()
398 .addReg(PPC::X1)); in LowerPATCHPOINT()
407 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::LD) in LowerPATCHPOINT()
[all …]
DPPCHazardRecognizers.cpp68 if (!PredMCID || PredMCID->getSchedClass() != PPC::Sched::IIC_SprMTSPR) in isBCTRAfterSet()
83 namespace llvm { namespace PPC { extern int getNonRecordFormOpcode(uint16_t); } } namespace
97 case PPC::Sched::IIC_IntDivW: in mustComeFirst()
98 case PPC::Sched::IIC_IntDivD: in mustComeFirst()
99 case PPC::Sched::IIC_LdStLoadUpd: in mustComeFirst()
100 case PPC::Sched::IIC_LdStLDU: in mustComeFirst()
101 case PPC::Sched::IIC_LdStLFDU: in mustComeFirst()
102 case PPC::Sched::IIC_LdStLFDUX: in mustComeFirst()
103 case PPC::Sched::IIC_LdStLHA: in mustComeFirst()
104 case PPC::Sched::IIC_LdStLHAU: in mustComeFirst()
[all …]
DPPCBranchSelector.cpp143 if (I->getOpcode() == PPC::BCC && !I->getOperand(2).isImm()) in runOnMachineFunction()
145 else if ((I->getOpcode() == PPC::BC || I->getOpcode() == PPC::BCn) && in runOnMachineFunction()
148 else if ((I->getOpcode() == PPC::BDNZ8 || I->getOpcode() == PPC::BDNZ || in runOnMachineFunction()
149 I->getOpcode() == PPC::BDZ8 || I->getOpcode() == PPC::BDZ) && in runOnMachineFunction()
188 if (I->getOpcode() == PPC::BCC) { in runOnMachineFunction()
193 PPC::Predicate Pred = (PPC::Predicate)I->getOperand(0).getImm(); in runOnMachineFunction()
197 BuildMI(MBB, I, dl, TII->get(PPC::BCC)) in runOnMachineFunction()
198 .addImm(PPC::InvertPredicate(Pred)).addReg(CRReg).addImm(2); in runOnMachineFunction()
199 } else if (I->getOpcode() == PPC::BC) { in runOnMachineFunction()
201 BuildMI(MBB, I, dl, TII->get(PPC::BCn)).addReg(CRBit).addImm(2); in runOnMachineFunction()
[all …]
DPPCTLSDynamicCall.cpp61 if (MI->getOpcode() != PPC::ADDItlsgdLADDR && in processBlock()
62 MI->getOpcode() != PPC::ADDItlsldLADDR && in processBlock()
63 MI->getOpcode() != PPC::ADDItlsgdLADDR32 && in processBlock()
64 MI->getOpcode() != PPC::ADDItlsldLADDR32) { in processBlock()
74 unsigned GPR3 = Is64Bit ? PPC::X3 : PPC::R3; in processBlock()
84 case PPC::ADDItlsgdLADDR: in processBlock()
85 Opc1 = PPC::ADDItlsgdL; in processBlock()
86 Opc2 = PPC::GETtlsADDR; in processBlock()
88 case PPC::ADDItlsldLADDR: in processBlock()
89 Opc1 = PPC::ADDItlsldL; in processBlock()
[all …]
DPPCVSXCopy.cpp69 return IsRegInClass(Reg, &PPC::VSRCRegClass, MRI); in IsVSReg()
73 return IsRegInClass(Reg, &PPC::VRRCRegClass, MRI); in IsVRReg()
77 return IsRegInClass(Reg, &PPC::F8RCRegClass, MRI); in IsF8Reg()
81 return IsRegInClass(Reg, &PPC::VSFRCRegClass, MRI); in IsVSFReg()
85 return IsRegInClass(Reg, &PPC::VSSRCRegClass, MRI); in IsVSSReg()
108 IsVRReg(SrcMO.getReg(), MRI) ? &PPC::VSHRCRegClass : in processBlock()
109 &PPC::VSLRCRegClass; in processBlock()
122 .addImm(IsVRReg(SrcMO.getReg(), MRI) ? PPC::sub_128 : in processBlock()
123 PPC::sub_64); in processBlock()
133 IsVRReg(DstMO.getReg(), MRI) ? &PPC::VSHRCRegClass : in processBlock()
[all …]
DPPCISelLowering.cpp70 addRegisterClass(MVT::i32, &PPC::GPRCRegClass); in PPCTargetLowering()
72 addRegisterClass(MVT::f32, &PPC::F4RCRegClass); in PPCTargetLowering()
73 addRegisterClass(MVT::f64, &PPC::F8RCRegClass); in PPCTargetLowering()
129 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass); in PPCTargetLowering()
394 addRegisterClass(MVT::i64, &PPC::G8RCRegClass); in PPCTargetLowering()
518 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass); in PPCTargetLowering()
519 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass); in PPCTargetLowering()
520 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass); in PPCTargetLowering()
521 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass); in PPCTargetLowering()
604 addRegisterClass(MVT::f32, &PPC::VSSRCRegClass); in PPCTargetLowering()
[all …]
DPPCEarlyReturn.cpp66 (I->getOpcode() != PPC::BLR && I->getOpcode() != PPC::BLR8) || in processBlock()
82 if (J->getOpcode() == PPC::B) { in processBlock()
94 } else if (J->getOpcode() == PPC::BCC) { in processBlock()
98 BuildMI(**PI, J, J->getDebugLoc(), TII->get(PPC::BCCLR)) in processBlock()
108 } else if (J->getOpcode() == PPC::BC || J->getOpcode() == PPC::BCn) { in processBlock()
114 TII->get(J->getOpcode() == PPC::BC ? PPC::BCLR : PPC::BCLRn)) in processBlock()
DPPCSubtarget.cpp60 DarwinDirective = PPC::DIR_NONE; in initializeEnvironment()
163 case PPC::DIR_440: in needsAggressiveScheduling()
164 case PPC::DIR_A2: in needsAggressiveScheduling()
165 case PPC::DIR_E500mc: in needsAggressiveScheduling()
166 case PPC::DIR_E5500: in needsAggressiveScheduling()
167 case PPC::DIR_PWR7: in needsAggressiveScheduling()
168 case PPC::DIR_PWR8: in needsAggressiveScheduling()
190 &PPC::G8RCRegClass : &PPC::GPRCRegClass); in getCriticalPathRCs()
/external/llvm/lib/Target/PowerPC/InstPrinter/
DPPCInstPrinter.cpp59 if (MI->getOpcode() == PPC::RLWINM) { in printInst()
82 if ((MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) && in printInst()
92 if (MI->getOpcode() == PPC::RLDICR) { in printInst()
115 if (MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) { in printInst()
118 if (MI->getOpcode() == PPC::DCBTST) in printInst()
124 bool IsBookE = STI.getFeatureBits()[PPC::FeatureBookE]; in printInst()
162 switch ((PPC::Predicate)Code) { in printPredicateOperand()
163 case PPC::PRED_LT_MINUS: in printPredicateOperand()
164 case PPC::PRED_LT_PLUS: in printPredicateOperand()
165 case PPC::PRED_LT: in printPredicateOperand()
[all …]
/external/llvm/test/tools/llvm-readobj/
Drelocations.test14 RUN: | FileCheck %s -check-prefix MACHO-PPC
60 MACHO-PPC: Relocations [
61 MACHO-PPC-NEXT: Section __text {
62 MACHO-PPC-NEXT: Relocation {
63 MACHO-PPC-NEXT: Offset: 0x24
64 MACHO-PPC-NEXT: PCRel: 0
65 MACHO-PPC-NEXT: Length: 2
66 MACHO-PPC-NEXT: Type: PPC_RELOC_LO16_SECTDIFF (11)
67 MACHO-PPC-NEXT: Value: 0x64
68 MACHO-PPC-NEXT: }
[all …]
Dsections-ext.test10 RUN: | FileCheck %s -check-prefix MACHO-PPC
284 MACHO-PPC: Sections [
285 MACHO-PPC-NEXT: Section {
286 MACHO-PPC-NEXT: Index: 0
287 MACHO-PPC-NEXT: Name: __text (5F 5F 74 65 78 74 00 00 00 00 00 00 00 00 00 00)
288 MACHO-PPC-NEXT: Segment: __TEXT (5F 5F 54 45 58 54 00 00 00 00 00 00 00 00 00 00)
289 MACHO-PPC-NEXT: Address: 0x0
290 MACHO-PPC-NEXT: Size: 0x3C
291 MACHO-PPC-NEXT: Offset: 528
292 MACHO-PPC-NEXT: Alignment: 2
[all …]
Dsections.test12 RUN: | FileCheck %s -check-prefix MACHO-PPC
196 MACHO-PPC: Sections [
197 MACHO-PPC-NEXT: Section {
198 MACHO-PPC-NEXT: Index: 0
199 MACHO-PPC-NEXT: Name: __text (5F 5F 74 65 78 74 00 00 00 00 00 00 00 00 00 00)
200 MACHO-PPC-NEXT: Segment: __TEXT (5F 5F 54 45 58 54 00 00 00 00 00 00 00 00 00 00)
201 MACHO-PPC-NEXT: Address: 0x0
202 MACHO-PPC-NEXT: Size: 0x3C
203 MACHO-PPC-NEXT: Offset: 528
204 MACHO-PPC-NEXT: Alignment: 2
[all …]
Delf-gnuhash.test17 RUN: llvm-readobj -gnu-hash-table %p/Inputs/gnuhash.so.elf-ppc | FileCheck %s -check-prefix PPC
42 PPC: Arch: powerpc
43 PPC: GnuHashTable {
44 PPC-NEXT: Num Buckets: 3
45 PPC-NEXT: First Hashed Symbol Index: 1
46 PPC-NEXT: Num Mask Words: 1
47 PPC-NEXT: Shift Count: 5
48 PPC-NEXT: Bloom Filter: [0x3D00460A]
49 PPC-NEXT: Buckets: [1, 5, 0]
50 PPC-NEXT: Values: [0xEEBEC3A, 0xB887388, 0xECD54542, 0x7C92E3BB, 0x1C5871D9]
[all …]

1234567