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Searched refs:Pat (Results 1 – 25 of 89) sorted by relevance

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/external/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrMemory.td46 def : Pat<(i32 (load I32:$addr)), (LOAD_I32 0, $addr)>;
47 def : Pat<(i64 (load I32:$addr)), (LOAD_I64 0, $addr)>;
48 def : Pat<(f32 (load I32:$addr)), (LOAD_F32 0, $addr)>;
49 def : Pat<(f64 (load I32:$addr)), (LOAD_F64 0, $addr)>;
52 def : Pat<(i32 (load (regPlusImm imm:$off, I32:$addr))),
54 def : Pat<(i64 (load (regPlusImm imm:$off, I32:$addr))),
56 def : Pat<(f32 (load (regPlusImm imm:$off, I32:$addr))),
58 def : Pat<(f64 (load (regPlusImm imm:$off, I32:$addr))),
60 def : Pat<(i32 (load (regPlusImm tglobaladdr:$off, I32:$addr))),
62 def : Pat<(i64 (load (regPlusImm tglobaladdr:$off, I32:$addr))),
[all …]
DWebAssemblyInstrFloat.td42 def : Pat<(fcopysign F64:$lhs, F32:$rhs),
44 def : Pat<(fcopysign F32:$lhs, F64:$rhs),
48 def : Pat<(frint f32:$src), (NEAREST_F32 f32:$src)>;
49 def : Pat<(frint f64:$src), (NEAREST_F64 f64:$src)>;
65 def : Pat<(seteq f32:$lhs, f32:$rhs), (EQ_F32 f32:$lhs, f32:$rhs)>;
66 def : Pat<(setne f32:$lhs, f32:$rhs), (NE_F32 f32:$lhs, f32:$rhs)>;
67 def : Pat<(setlt f32:$lhs, f32:$rhs), (LT_F32 f32:$lhs, f32:$rhs)>;
68 def : Pat<(setle f32:$lhs, f32:$rhs), (LE_F32 f32:$lhs, f32:$rhs)>;
69 def : Pat<(setgt f32:$lhs, f32:$rhs), (GT_F32 f32:$lhs, f32:$rhs)>;
70 def : Pat<(setge f32:$lhs, f32:$rhs), (GE_F32 f32:$lhs, f32:$rhs)>;
[all …]
DWebAssemblyInstrCall.td53 def : Pat<(i32 (WebAssemblycall1 (WebAssemblywrapper tglobaladdr:$callee))),
55 def : Pat<(i64 (WebAssemblycall1 (WebAssemblywrapper tglobaladdr:$callee))),
57 def : Pat<(f32 (WebAssemblycall1 (WebAssemblywrapper tglobaladdr:$callee))),
59 def : Pat<(f64 (WebAssemblycall1 (WebAssemblywrapper tglobaladdr:$callee))),
61 def : Pat<(WebAssemblycall0 (WebAssemblywrapper tglobaladdr:$callee)),
65 def : Pat<(i32 (WebAssemblycall1 (WebAssemblywrapper texternalsym:$callee))),
67 def : Pat<(i64 (WebAssemblycall1 (WebAssemblywrapper texternalsym:$callee))),
69 def : Pat<(f32 (WebAssemblycall1 (WebAssemblywrapper texternalsym:$callee))),
71 def : Pat<(f64 (WebAssemblycall1 (WebAssemblywrapper texternalsym:$callee))),
73 def : Pat<(WebAssemblycall0 (WebAssemblywrapper texternalsym:$callee)),
DWebAssemblyInstrInteger.td60 def : Pat<(ctlz_zero_undef I32:$src), (CLZ_I32 I32:$src)>;
61 def : Pat<(ctlz_zero_undef I64:$src), (CLZ_I64 I64:$src)>;
62 def : Pat<(cttz_zero_undef I32:$src), (CTZ_I32 I32:$src)>;
63 def : Pat<(cttz_zero_undef I64:$src), (CTZ_I64 I64:$src)>;
79 def : Pat<(select (i32 (setne I32:$cond, 0)), I32:$lhs, I32:$rhs),
81 def : Pat<(select (i32 (setne I32:$cond, 0)), I64:$lhs, I64:$rhs),
85 def : Pat<(select (i32 (seteq I32:$cond, 0)), I32:$lhs, I32:$rhs),
87 def : Pat<(select (i32 (seteq I32:$cond, 0)), I64:$lhs, I64:$rhs),
/external/llvm/lib/Target/AArch64/
DAArch64InstrAtomics.td17 def : Pat<(atomic_fence (i64 4), (imm)), (DMB (i32 0x9))>;
18 def : Pat<(atomic_fence (imm), (imm)), (DMB (i32 0xb))>;
44 def : Pat<(acquiring_load<atomic_load_8> GPR64sp:$ptr), (LDARB GPR64sp:$ptr)>;
45 def : Pat<(relaxed_load<atomic_load_8> (ro_Windexed8 GPR64sp:$Rn, GPR32:$Rm,
48 def : Pat<(relaxed_load<atomic_load_8> (ro_Xindexed8 GPR64sp:$Rn, GPR64:$Rm,
51 def : Pat<(relaxed_load<atomic_load_8> (am_indexed8 GPR64sp:$Rn,
54 def : Pat<(relaxed_load<atomic_load_8>
59 def : Pat<(acquiring_load<atomic_load_16> GPR64sp:$ptr), (LDARH GPR64sp:$ptr)>;
60 def : Pat<(relaxed_load<atomic_load_16> (ro_Windexed16 GPR64sp:$Rn, GPR32:$Rm,
63 def : Pat<(relaxed_load<atomic_load_16> (ro_Xindexed16 GPR64sp:$Rn, GPR64:$Rm,
[all …]
DAArch64InstrInfo.td366 def : Pat<(AArch64LOADgot tglobaltlsaddr:$addr),
369 def : Pat<(AArch64LOADgot texternalsym:$addr),
372 def : Pat<(AArch64LOADgot tconstpool:$addr),
417 def : Pat<(AArch64threadpointer), (MRS 0xde82)>;
421 def : Pat<(readcyclecounter), (MRS 0xdce8)>;
535 def : Pat<(i64 i64imm_32bit:$src),
550 def : Pat<(f32 fpimm:$in),
552 def : Pat<(f64 fpimm:$in),
558 def : Pat<(AArch64WrapperLarge tglobaladdr:$g3, tglobaladdr:$g2,
565 def : Pat<(AArch64WrapperLarge tblockaddress:$g3, tblockaddress:$g2,
[all …]
/external/llvm/lib/Target/PowerPC/
DPPCInstrHTM.td96 def : Pat<(int_ppc_tbegin i32:$R),
102 def : Pat<(int_ppc_tend i32:$R),
106 def : Pat<(int_ppc_tabort i32:$R),
109 def : Pat<(int_ppc_tabortwc i32:$TO, i32:$RA, i32:$RB),
112 def : Pat<(int_ppc_tabortwci i32:$TO, i32:$RA, i32:$SI),
115 def : Pat<(int_ppc_tabortdc i32:$TO, i32:$RA, i32:$RB),
118 def : Pat<(int_ppc_tabortdci i32:$TO, i32:$RA, i32:$SI),
121 def : Pat<(int_ppc_tcheck),
124 def : Pat<(int_ppc_treclaim i32:$RA),
127 def : Pat<(int_ppc_trechkpt),
[all …]
DPPCInstrQPX.td837 def : Pat<(v4f64 (scalar_to_vector f64:$A)),
839 def : Pat<(v4f32 (scalar_to_vector f32:$A)),
842 def : Pat<(f64 (extractelt v4f64:$S, 0)),
844 def : Pat<(f32 (extractelt v4f32:$S, 0)),
847 def : Pat<(f64 (extractelt v4f64:$S, 1)),
849 def : Pat<(f64 (extractelt v4f64:$S, 2)),
851 def : Pat<(f64 (extractelt v4f64:$S, 3)),
854 def : Pat<(f32 (extractelt v4f32:$S, 1)),
856 def : Pat<(f32 (extractelt v4f32:$S, 2)),
858 def : Pat<(f32 (extractelt v4f32:$S, 3)),
[all …]
DPPCInstrVSX.td835 def : Pat<(v2f64 (scalar_to_vector f64:$A)),
838 def : Pat<(f64 (extractelt v2f64:$S, 0)),
840 def : Pat<(f64 (extractelt v2f64:$S, 1)),
845 def : Pat<(v2f64 (scalar_to_vector f64:$A)),
849 def : Pat<(f64 (extractelt v2f64:$S, 0)),
851 def : Pat<(f64 (extractelt v2f64:$S, 1)),
856 def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
858 def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B),
861 def : Pat<(fma (fneg v2f64:$A), v2f64:$C, v2f64:$B),
863 def : Pat<(fma v2f64:$A, (fneg v2f64:$C), v2f64:$B),
[all …]
DPPCInstrAltivec.td848 def : Pat<(v4i32 (load xoaddr:$src)), (LVX xoaddr:$src)>;
851 def : Pat<(store v4i32:$rS, xoaddr:$dst),
855 def : Pat<(v16i8 (bitconvert (v8i16 VRRC:$src))), (v16i8 VRRC:$src)>;
856 def : Pat<(v16i8 (bitconvert (v4i32 VRRC:$src))), (v16i8 VRRC:$src)>;
857 def : Pat<(v16i8 (bitconvert (v4f32 VRRC:$src))), (v16i8 VRRC:$src)>;
858 def : Pat<(v16i8 (bitconvert (v2i64 VRRC:$src))), (v16i8 VRRC:$src)>;
859 def : Pat<(v16i8 (bitconvert (v1i128 VRRC:$src))), (v16i8 VRRC:$src)>;
861 def : Pat<(v8i16 (bitconvert (v16i8 VRRC:$src))), (v8i16 VRRC:$src)>;
862 def : Pat<(v8i16 (bitconvert (v4i32 VRRC:$src))), (v8i16 VRRC:$src)>;
863 def : Pat<(v8i16 (bitconvert (v4f32 VRRC:$src))), (v8i16 VRRC:$src)>;
[all …]
/external/llvm/lib/Target/X86/
DX86InstrCompiler.td11 // as well as Pat patterns used during instruction selection.
55 def : Pat<(X86callseq_start timm:$amt1),
74 def : Pat<(X86callseq_start timm:$amt1),
259 def : Pat<(i8 0), (EXTRACT_SUBREG (MOV32r0), sub_8bit)>;
260 def : Pat<(i16 0), (EXTRACT_SUBREG (MOV32r0), sub_16bit)>;
261 def : Pat<(i64 0), (SUBREG_TO_REG (i64 0), (MOV32r0), sub_32bit)> {
277 def : Pat<(i16 1), (EXTRACT_SUBREG (MOV32r1), sub_16bit)>;
278 def : Pat<(i16 -1), (EXTRACT_SUBREG (MOV32r_1), sub_16bit)>;
306 def : Pat<(i64 mov64imm32:$src),
311 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
[all …]
DX86InstrSSE.td333 def : Pat<(f32 (extractelt (v4f32 VR128:$src), (iPTR 0))),
335 def : Pat<(f64 (extractelt (v2f64 VR128:$src), (iPTR 0))),
340 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (iPTR 0))),
342 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (iPTR 0))),
345 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (iPTR 0))),
347 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (iPTR 0))),
350 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (iPTR 0))),
352 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (iPTR 0))),
358 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)),
360 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)),
[all …]
DX86InstrAVX512.td194 // Prefer over VMOV*rrk Pat<>
204 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
376 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
377 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
378 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
379 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
380 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
381 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
382 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
383 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfoVector.td25 def : Pat <(b (bitconvert (a IntRegs:$src))),
27 def : Pat <(a (bitconvert (b IntRegs:$src))),
32 def : Pat <(b (bitconvert (a DoubleRegs:$src))),
34 def : Pat <(a (bitconvert (b DoubleRegs:$src))),
39 def : Pat <(b (bitconvert (a VectorRegs:$src))),
41 def : Pat <(a (bitconvert (b VectorRegs:$src))),
46 def : Pat <(b (bitconvert (a VecDblRegs:$src))),
48 def : Pat <(a (bitconvert (b VecDblRegs:$src))),
53 def : Pat <(b (bitconvert (a VecPredRegs:$src))),
55 def : Pat <(a (bitconvert (b VectorRegs:$src))),
[all …]
DHexagonIntrinsicsV60.td63 def : Pat < (v16i32 (int_hexagon_V6_lo (v32i32 VecDblRegs:$src1))),
67 def : Pat < (v16i32 (int_hexagon_V6_hi (v32i32 VecDblRegs:$src1))),
71 def : Pat < (v32i32 (int_hexagon_V6_lo_128B (v64i32 VecDblRegs128B:$src1))),
76 def : Pat < (v32i32 (int_hexagon_V6_hi_128B (v64i32 VecDblRegs128B:$src1))),
82 def : Pat <(v512i1 (bitconvert (v16i32 VectorRegs:$src1))),
87 def : Pat <(v512i1 (bitconvert (v32i16 VectorRegs:$src1))),
92 def : Pat <(v512i1 (bitconvert (v64i8 VectorRegs:$src1))),
97 def : Pat <(v512i1 (bitconvert (v8i64 VectorRegs:$src1))),
102 def : Pat <(v16i32 (bitconvert (v512i1 VecPredRegs:$src1))),
107 def : Pat <(v32i16 (bitconvert (v512i1 VecPredRegs:$src1))),
[all …]
DHexagonInstrInfoV5.td179 def: Pat<(f32 (fadd F32:$src1, F32:$src2)),
182 def: Pat<(f32 (fsub F32:$src1, F32:$src2)),
185 def: Pat<(f32 (fmul F32:$src1, F32:$src2)),
194 def: Pat<(f32 (select (i1 (setolt F32:$src1, F32:$src2)),
198 def: Pat<(f32 (select (i1 (setogt F32:$src1, F32:$src2)),
202 def: Pat<(f32 (select (i1 (setogt F32:$src1, F32:$src2)),
206 def: Pat<(f32 (select (i1 (setolt F32:$src1, F32:$src2)),
289 def: Pat<(i1 (cmpOp F32:$src1, F32:$src2)),
292 def: Pat<(i1 (cmpOp F64:$src1, F64:$src2)),
306 def: Pat<(i1 (cmpOp F32:$src1, F32:$src2)),
[all …]
DHexagonSelectCCInfo.td14 def : Pat <(i32 (selectcc IntRegs:$lhs, IntRegs:$rhs, IntRegs:$tval,
19 def : Pat <(i32 (selectcc IntRegs:$lhs, IntRegs:$rhs, IntRegs:$tval,
24 def : Pat <(i32 (selectcc IntRegs:$lhs, IntRegs:$rhs, IntRegs:$tval,
29 def : Pat <(i32 (selectcc IntRegs:$lhs, IntRegs:$rhs, IntRegs:$tval,
36 def : Pat <(i32 (selectcc IntRegs:$lhs, IntRegs:$rhs, IntRegs:$tval,
42 def : Pat <(i32 (selectcc IntRegs:$lhs, IntRegs:$rhs, IntRegs:$tval,
48 def : Pat <(i32 (selectcc IntRegs:$lhs, IntRegs:$rhs, IntRegs:$tval,
53 def : Pat <(i32 (selectcc IntRegs:$lhs, IntRegs:$rhs, IntRegs:$tval,
62 def : Pat <(i32 (selectcc IntRegs:$lhs, IntRegs:$rhs, IntRegs:$tval,
67 def : Pat <(i32 (selectcc IntRegs:$lhs, IntRegs:$rhs, IntRegs:$tval,
[all …]
DHexagonIntrinsics.td17 : Pat <(IntID imm:$Is),
21 : Pat <(IntID I32:$Rs),
25 : Pat <(IntID I64:$Rs),
29 : Pat<(IntID Imm1:$Is, Imm2:$It),
33 : Pat<(IntID I32:$Rs, ImmPred:$It),
37 : Pat<(IntID ImmPred:$Is, I32:$Rt),
41 : Pat<(IntID I64:$Rs, imm:$It),
45 : Pat<(IntID I32:$Rs, I64:$Rt),
49 : Pat <(IntID I32:$Rs, I32:$Rt),
53 : Pat <(IntID I64:$Rs, I64:$Rt),
[all …]
/external/llvm/lib/Target/Sparc/
DSparcInstr64Bit.td22 def : Pat<(i64 (anyext i32:$val)), (COPY_TO_REGCLASS $val, I64Regs)>;
23 def : Pat<(i32 (trunc i64:$val)), (COPY_TO_REGCLASS $val, IntRegs)>;
40 def : Pat<(i64 (zext i32:$val)), (SRLri $val, 0)>;
41 def : Pat<(i64 (sext i32:$val)), (SRAri $val, 0)>;
43 def : Pat<(i64 (and i64:$val, 0xffffffff)), (SRLri $val, 0)>;
44 def : Pat<(i64 (sext_inreg i64:$val, i32)), (SRAri $val, 0)>;
68 def : Pat<(i64 simm13:$val), (ORri (i64 G0), (as_i32imm $val))>;
69 def : Pat<(i64 SETHIimm:$val), (SETHIi (HI22 $val))>;
75 def : Pat<(i64 uimm32:$val), (ORri (SETHIi (HI22 $val)), (LO10 $val))>,
93 def : Pat<(i64 nimm33:$val), (XORri (SETHIi (HIX22 $val)), (LOX10 $val))>,
[all …]
/external/llvm/lib/Target/SystemZ/
DSystemZInstrFP.td82 def : Pat<(fcopysign FP32:$src1, FP128:$src2),
91 def : Pat<(fcopysign FP64:$src1, FP128:$src2),
97 : Pat<(fcopysign FP128:$src1, cls:$src2),
164 def : Pat<(f32 (fround FP128:$src)),
166 def : Pat<(f64 (fround FP128:$src)),
198 def : Pat<(f32 (uint_to_fp GR32:$src)), (CELFBR 0, GR32:$src, 0)>;
199 def : Pat<(f64 (uint_to_fp GR32:$src)), (CDLFBR 0, GR32:$src, 0)>;
200 def : Pat<(f128 (uint_to_fp GR32:$src)), (CXLFBR 0, GR32:$src, 0)>;
202 def : Pat<(f32 (uint_to_fp GR64:$src)), (CELGBR 0, GR64:$src, 0)>;
203 def : Pat<(f64 (uint_to_fp GR64:$src)), (CDLGBR 0, GR64:$src, 0)>;
[all …]
DSystemZPatterns.td13 def : Pat<(operator (sext (i32 GR32:$src))),
15 def : Pat<(operator (sext_inreg GR64:$src, i32)),
24 def : Pat<(operator cls:$src1, (sext GR32:$src2)),
26 def : Pat<(operator cls:$src1, (sext_inreg GR64:$src2, i32)),
33 def : Pat<(operator cls:$src1, (zext GR32:$src2)),
35 def : Pat<(operator cls:$src1, (and GR64:$src2, 0xffffffff)),
46 : Pat<(store (operator (load mode:$addr), imm:$src), mode:$addr),
61 def : Pat<(!cast<SDPatternOperator>("or_as_"##type)
64 def : Pat<(!cast<SDPatternOperator>("or_as_rev"##type)
73 : Pat<(operator GR64:$R1, mode:$XBD2),
[all …]
DSystemZInstrVector.td45 : Pat<(i32 (z_vector_extract (type VR128:$vec), shift12only:$index)),
126 def : Pat<(v4f32 (z_replicate_loadf32 bdxaddr12only:$addr)),
128 def : Pat<(v2f64 (z_replicate_loadf64 bdxaddr12only:$addr)),
143 def : Pat<(v4f32 (z_vllezf32 bdxaddr12only:$addr)),
145 def : Pat<(v2f64 (z_vllezf64 bdxaddr12only:$addr)),
153 def : Pat<(z_vlef32 (v4f32 VR128:$val), bdxaddr12only:$addr, imm32zx2:$index),
155 def : Pat<(z_vlef64 (v2f64 VR128:$val), bdxaddr12only:$addr, imm32zx1:$index),
168 def : Pat<(vectype (z_vector_insert
171 def : Pat<(vectype (scalar_to_vector
201 def : Pat<(z_vstef32 (v4f32 VR128:$val), bdxaddr12only:$addr,
[all …]
/external/llvm/lib/Target/XCore/
DXCoreInstrInfo.td1117 def : Pat<(XCoreBranchLink texternalsym:$addr), (BLRF_lu10 texternalsym:$addr)>;
1120 def : Pat<(sext_inreg GRRegs:$b, i1), (SEXT_rus GRRegs:$b, 1)>;
1121 def : Pat<(sext_inreg GRRegs:$b, i8), (SEXT_rus GRRegs:$b, 8)>;
1122 def : Pat<(sext_inreg GRRegs:$b, i16), (SEXT_rus GRRegs:$b, 16)>;
1125 def : Pat<(zextloadi8 (add GRRegs:$addr, GRRegs:$offset)),
1127 def : Pat<(zextloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>;
1129 def : Pat<(sextloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)),
1131 def : Pat<(sextloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>;
1133 def : Pat<(load (ldawf GRRegs:$addr, GRRegs:$offset)),
1135 def : Pat<(load (add GRRegs:$addr, immUs4:$offset)),
[all …]
/external/llvm/lib/Target/NVPTX/
DNVPTXInstrInfo.td504 def : Pat<(shl (sext Int32Regs:$a), (i32 Int5Const:$b)),
507 def : Pat<(shl (zext Int32Regs:$a), (i32 Int5Const:$b)),
511 def : Pat<(shl (sext Int16Regs:$a), (i16 Int4Const:$b)),
514 def : Pat<(shl (zext Int16Regs:$a), (i16 Int4Const:$b)),
518 def : Pat<(mul (sext Int32Regs:$a), (sext Int32Regs:$b)),
521 def : Pat<(mul (sext Int32Regs:$a), (i64 SInt32Const:$b)),
525 def : Pat<(mul (zext Int32Regs:$a), (zext Int32Regs:$b)),
528 def : Pat<(mul (zext Int32Regs:$a), (i64 UInt32Const:$b)),
532 def : Pat<(mul (sext Int16Regs:$a), (sext Int16Regs:$b)),
535 def : Pat<(mul (sext Int16Regs:$a), (i32 SInt16Const:$b)),
[all …]
DNVPTXIntrinsics.td90 def : Pat<(int_nvvm_fmin_f immFloat1,
93 def : Pat<(int_nvvm_fmin_f immFloat1,
96 def : Pat<(int_nvvm_fmin_f
99 def : Pat<(int_nvvm_fmin_f
103 def : Pat<(int_nvvm_fmin_d immDouble1,
106 def : Pat<(int_nvvm_fmin_d immDouble1,
109 def : Pat<(int_nvvm_fmin_d
112 def : Pat<(int_nvvm_fmin_d
302 def : Pat<(int_nvvm_floor_ftz_f Float32Regs:$a),
304 def : Pat<(int_nvvm_floor_f Float32Regs:$a),
[all …]

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