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Searched refs:PredReg (Results 1 – 24 of 24) sorted by relevance

/external/llvm/lib/Target/ARM/
DARMLoadStoreOptimizer.cpp136 ARMCC::CondCodes Pred, unsigned PredReg);
139 bool BaseKill, unsigned Opcode, ARMCC::CondCodes Pred, unsigned PredReg,
143 bool BaseKill, unsigned Opcode, ARMCC::CondCodes Pred, unsigned PredReg,
444 ARMCC::CondCodes Pred, unsigned PredReg) { in UpdateBaseRegUses() argument
512 .addReg(Base).addImm(WordOffset * 4).addImm(Pred).addReg(PredReg); in UpdateBaseRegUses()
530 .addReg(Base).addImm(WordOffset * 4).addImm(Pred).addReg(PredReg); in UpdateBaseRegUses()
579 bool BaseKill, unsigned Opcode, ARMCC::CondCodes Pred, unsigned PredReg, in CreateLoadStoreMulti() argument
694 .addImm(Pred).addReg(PredReg); in CreateLoadStoreMulti()
704 .addImm(Pred).addReg(PredReg); in CreateLoadStoreMulti()
709 .addImm(Pred).addReg(PredReg); in CreateLoadStoreMulti()
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DThumb2InstrInfo.cpp60 unsigned PredReg = 0; in ReplaceTailWithBranchTo() local
61 ARMCC::CondCodes CC = getInstrPredicate(Tail, PredReg); in ReplaceTailWithBranchTo()
108 unsigned PredReg = 0; in isLegalToSplitMBBAt() local
109 return getITInstrPredicate(MBBI, PredReg) == ARMCC::AL; in isLegalToSplitMBBAt()
219 ARMCC::CondCodes Pred, unsigned PredReg, in emitT2RegPlusImmediate() argument
224 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); in emitT2RegPlusImmediate()
241 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); in emitT2RegPlusImmediate()
248 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); in emitT2RegPlusImmediate()
257 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) in emitT2RegPlusImmediate()
268 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) in emitT2RegPlusImmediate()
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DThumbRegisterInfo.cpp66 ARMCC::CondCodes Pred, unsigned PredReg, in emitThumb1LoadConstPool() argument
78 .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg) in emitThumb1LoadConstPool()
86 ARMCC::CondCodes Pred, unsigned PredReg, in emitThumb2LoadConstPool() argument
106 unsigned PredReg, unsigned MIFlags) const { in emitLoadConstPool() argument
113 PredReg, MIFlags); in emitLoadConstPool()
116 PredReg, MIFlags); in emitLoadConstPool()
DMLxExpansionPass.cpp285 unsigned PredReg = MI->getOperand(++NextOp).getReg(); in ExpandFPMLxInstruction() local
298 MIB.addImm(Pred).addReg(PredReg); in ExpandFPMLxInstruction()
310 MIB.addImm(Pred).addReg(PredReg); in ExpandFPMLxInstruction()
DARMBaseRegisterInfo.cpp386 unsigned PredReg, unsigned MIFlags) const { in emitLoadConstPool() argument
397 .addImm(0).addImm(Pred).addReg(PredReg) in emitLoadConstPool()
736 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); in eliminateFrameIndex() local
744 Offset, Pred, PredReg, TII); in eliminateFrameIndex()
748 Offset, Pred, PredReg, TII); in eliminateFrameIndex()
DThumbRegisterInfo.h43 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0,
DThumb2InstrInfo.h73 ARMCC::CondCodes getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
DThumb2ITBlockPass.cpp184 unsigned PredReg = 0; in InsertITInstructions() local
185 ARMCC::CondCodes CC = getITInstrPredicate(MI, PredReg); in InsertITInstructions()
DThumb2SizeReduction.cpp599 unsigned PredReg = 0; in ReduceSpecial() local
600 if (getInstrPredicate(MI, PredReg) == ARMCC::AL) { in ReduceSpecial()
704 unsigned PredReg = 0; in ReduceTo2Addr() local
705 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); in ReduceTo2Addr()
800 unsigned PredReg = 0; in ReduceToNarrow() local
801 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); in ReduceToNarrow()
DARMBaseInstrInfo.h450 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
471 ARMCC::CondCodes Pred, unsigned PredReg,
477 ARMCC::CondCodes Pred, unsigned PredReg,
DARMFrameLowering.cpp129 unsigned PredReg = 0) { in emitRegPlusImmediate() argument
132 Pred, PredReg, TII, MIFlags); in emitRegPlusImmediate()
135 Pred, PredReg, TII, MIFlags); in emitRegPlusImmediate()
143 unsigned PredReg = 0) { in emitSPUpdate() argument
145 MIFlags, Pred, PredReg); in emitSPUpdate()
1760 unsigned PredReg = Old->getOperand(2).getReg(); in eliminateCallFramePseudoInstr() local
1762 Pred, PredReg); in eliminateCallFramePseudoInstr()
1765 unsigned PredReg = Old->getOperand(3).getReg(); in eliminateCallFramePseudoInstr() local
1768 Pred, PredReg); in eliminateCallFramePseudoInstr()
DARMBaseRegisterInfo.h164 unsigned PredReg = 0,
DARMConstantIslandPass.cpp1486 unsigned PredReg = 0; in createNewWater() local
1487 ARMCC::CondCodes CC = getITInstrPredicate(MI, PredReg); in createNewWater()
1493 DEBUG(unsigned PredReg; in createNewWater()
1494 assert(!isThumb || getITInstrPredicate(MI, PredReg) == ARMCC::AL)); in createNewWater()
1942 unsigned PredReg = 0; in optimizeThumb2Branches() local
1943 ARMCC::CondCodes Pred = getInstrPredicate(Br.MI, PredReg); in optimizeThumb2Branches()
1961 Pred = getInstrPredicate(CmpMI, PredReg); in optimizeThumb2Branches()
DARMExpandPseudoInsts.cpp653 unsigned PredReg = 0; in ExpandMOV32BitImm() local
654 ARMCC::CondCodes Pred = getInstrPredicate(&MI, PredReg); in ExpandMOV32BitImm()
681 LO16.addImm(Pred).addReg(PredReg).addReg(0); in ExpandMOV32BitImm()
682 HI16.addImm(Pred).addReg(PredReg).addReg(0); in ExpandMOV32BitImm()
730 LO16.addImm(Pred).addReg(PredReg); in ExpandMOV32BitImm()
731 HI16.addImm(Pred).addReg(PredReg); in ExpandMOV32BitImm()
DARMBaseInstrInfo.cpp1720 unsigned PredReg = 0; in isProfitableToIfCvt() local
1721 ARMCC::CondCodes P = getInstrPredicate(CmpMI, PredReg); in isProfitableToIfCvt()
1777 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) { in getInstrPredicate() argument
1780 PredReg = 0; in getInstrPredicate()
1784 PredReg = MI->getOperand(PIdx+1).getReg(); in getInstrPredicate()
1808 unsigned PredReg = 0; in commuteInstructionImpl() local
1809 ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg); in commuteInstructionImpl()
1811 if (CC == ARMCC::AL || PredReg != ARM::CPSR) in commuteInstructionImpl()
1999 ARMCC::CondCodes Pred, unsigned PredReg, in emitARMRegPlusImmediate() argument
2004 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) in emitARMRegPlusImmediate()
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DARMISelDAGToDAG.cpp2516 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
2517 SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() }; in Select()
2786 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
2787 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; in Select()
2806 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
2807 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; in Select()
2825 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
2826 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; in Select()
/external/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCChecker.cpp59 unsigned PredReg = Hexagon::NoRegister; in init() local
69 PredReg = R; in init()
74 NewPreds.insert(PredReg); in init()
113 Defs[R].insert(PredSense(PredReg, isTrue)); in init()
152 CurDefs.insert(*SRI), Defs[*SRI].insert(PredSense(PredReg, isTrue)); in init()
165 Defs[*SRI].insert(PredSense(PredReg, isTrue)); in init()
181 … NewDefs[*SRI].push_back(NewSense::Def(PredReg, HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI), in init()
193 … NewDefs[*SRI].push_back(NewSense::Def(PredReg, HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI), in init()
217 NewUses[N] = NewSense::Use(PredReg, HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI)); in init()
560 if (Use.IsNVJ && (Def.IsFloat || Def.PredReg != 0)) in hasValidNewValueDef()
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DHexagonMCCompound.cpp182 unsigned PredReg = Predicate.getReg(); in getCompoundOp() local
184 assert((PredReg == Hexagon::P0) || (PredReg == Hexagon::P1) || in getCompoundOp()
185 (PredReg == Hexagon::P2) || (PredReg == Hexagon::P3)); in getCompoundOp()
192 return (PredReg == Hexagon::P0) ? fp0_jump_nt : fp1_jump_nt; in getCompoundOp()
194 return (PredReg == Hexagon::P0) ? fp0_jump_t : fp1_jump_t; in getCompoundOp()
196 return (PredReg == Hexagon::P0) ? tp0_jump_nt : tp1_jump_nt; in getCompoundOp()
198 return (PredReg == Hexagon::P0) ? tp0_jump_t : tp1_jump_t; in getCompoundOp()
DHexagonMCChecker.h99 unsigned PredReg; member
DHexagonMCDuplexInfo.cpp181 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg; in getDuplexCandidateGroup() local
475 PredReg = MCI.getOperand(1).getReg(); // P0 in getDuplexCandidateGroup()
477 Hexagon::P0 == PredReg && minConstant(MCI, 2) == 0) { in getDuplexCandidateGroup()
/external/llvm/lib/Target/Hexagon/
DHexagonGenPredicate.cpp97 bool isScalarPred(Register PredReg);
304 bool HexagonGenPredicate::isScalarPred(Register PredReg) { in isScalarPred() argument
306 WorkQ.push(PredReg); in isScalarPred()
DHexagonInstrInfo.h339 bool predCanBeUsedAsDotNew(const MachineInstr *MI, unsigned PredReg) const;
375 bool getPredReg(ArrayRef<MachineOperand> Cond, unsigned &PredReg,
DHexagonInstrInfo.cpp1073 unsigned PredReg, PredRegPos, PredRegFlags; in PredicateInstruction() local
1074 bool GotPredReg = getPredReg(Cond, PredReg, PredRegPos, PredRegFlags); in PredicateInstruction()
1077 T.addReg(PredReg, PredRegFlags); in PredicateInstruction()
1091 MRI.clearKillFlags(PredReg); in PredicateInstruction()
2659 unsigned PredReg) const { in predCanBeUsedAsDotNew()
2662 if (MO.isReg() && MO.isDef() && MO.isImplicit() && (MO.getReg() == PredReg)) in predCanBeUsedAsDotNew()
3639 unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const { in getPredReg() argument
3647 PredReg = Cond[1].getReg(); in getPredReg()
DHexagonHardwareLoops.cpp613 unsigned PredReg, PredPos, PredRegFlags; in getLoopTripCount() local
614 if (!TII->getPredReg(Cond, PredReg, PredPos, PredRegFlags)) in getLoopTripCount()
616 MachineInstr *CondI = MRI->getVRegDef(PredReg); in getLoopTripCount()