Searched refs:RCID (Results 1 – 8 of 8) sorted by relevance
203 int RCID = Desc.OpInfo[i].RegClass; in encodeInstruction() local204 const MCRegisterClass &RC = MRI.getRegClass(RCID); in encodeInstruction()265 int RCID = Desc.OpInfo[OpNo].RegClass; in getMachineOpValue() local266 const MCRegisterClass &RC = MRI.getRegClass(RCID); in getMachineOpValue()
65 bool isSGPRClassID(unsigned RCID) const { in isSGPRClassID()66 return isSGPRClass(getRegClass(RCID)); in isSGPRClassID()
1663 unsigned RCID = Desc.OpInfo[OpNo].RegClass; in getOpRegClass() local1664 return RI.getRegClass(RCID); in getOpRegClass()1684 unsigned RCID = get(MI->getOpcode()).OpInfo[OpIdx].RegClass; in legalizeOpWithMove() local1685 const TargetRegisterClass *RC = RI.getRegClass(RCID); in legalizeOpWithMove()
198 unsigned RCID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue(); in getOperandRegClass() local200 Subtarget->getRegisterInfo()->getRegClass(RCID); in getOperandRegClass()
311 int RCID = Desc.OpInfo[OpNo].RegClass; in printOperand() local312 if (RCID != -1) { in printOperand()313 const MCRegisterClass &ImmRC = MRI.getRegClass(RCID); in printOperand()
1108 unsigned RCID; in getRegClassConstraint() local1109 if (InlineAsm::hasRegClassConstraint(Flag, RCID)) in getRegClassConstraint()1110 return TRI->getRegClass(RCID); in getRegClassConstraint()1712 unsigned RCID = 0; in print() local1713 if (InlineAsm::hasRegClassConstraint(Flag, RCID)) { in print()1715 OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID)); in print()1717 OS << ":RC" << RCID; in print()
204 bool isRegClass(unsigned RCID) const { in isRegClass()205 return Reg.TRI->getRegClass(RCID).contains(getReg()); in isRegClass()583 int RCID = getRegClass(IsVgpr, RegWidth); in ParseRegister() local584 if (RCID == -1) in ParseRegister()587 const MCRegisterClass RC = TRI->getRegClass(RCID); in ParseRegister()
1369 unsigned RCID; in handleSpecialFP() local1387 if (InlineAsm::hasRegClassConstraint(Flags, RCID)) { in handleSpecialFP()