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Searched refs:ROR (Results 1 – 25 of 71) sorted by relevance

123

/external/v8/test/mjsunit/compiler/
Drotate.js47 function ROR(x, sa) { class
67 assertEquals(1 << ((2 % 32)), ROR(1, 30));
68 assertEquals(1 << ((2 % 32)), ROR(1, 30));
69 %OptimizeFunctionOnNextCall(ROR);
70 assertEquals(1 << ((2 % 32)), ROR(1, 30));
/external/boringssl/linux-arm/crypto/sha/
Dsha1-armv4-large.S44 add r7,r7,r3,ror#27 @ E+=ROR(A,27)
50 add r7,r7,r3,ror#27 @ E+=ROR(A,27)
69 add r6,r6,r7,ror#27 @ E+=ROR(A,27)
75 add r6,r6,r7,ror#27 @ E+=ROR(A,27)
94 add r5,r5,r6,ror#27 @ E+=ROR(A,27)
100 add r5,r5,r6,ror#27 @ E+=ROR(A,27)
119 add r4,r4,r5,ror#27 @ E+=ROR(A,27)
125 add r4,r4,r5,ror#27 @ E+=ROR(A,27)
144 add r3,r3,r4,ror#27 @ E+=ROR(A,27)
150 add r3,r3,r4,ror#27 @ E+=ROR(A,27)
[all …]
/external/valgrind/none/tests/arm/
Dv6media.stdout.exp3042 sxtab r0, r1, r2, ROR #24 :: rd 0x3141594e rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000…
3043 sxtab r0, r1, r2, ROR #16 :: rd 0x3141593f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000…
3044 sxtab r0, r1, r2, ROR #8 :: rd 0x3141594f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 …
3045 sxtab r0, r1, r2, ROR #0 :: rd 0x31415940 rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 …
3046 sxtab r0, r1, r2, ROR #24 :: rd 0x3141594e rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000…
3047 sxtab r0, r1, r2, ROR #16 :: rd 0x3141593f rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000…
3048 sxtab r0, r1, r2, ROR #8 :: rd 0x3141594f rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000 …
3049 sxtab r0, r1, r2, ROR #0 :: rd 0x314158c0 rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000 …
3050 sxtab r0, r1, r2, ROR #24 :: rd 0xf7b0b19c rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000…
3051 sxtab r0, r1, r2, ROR #24 :: rd 0x44de5cef rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000…
[all …]
Dv6intARM.stdout.exp295 ROR
349 ROR immediate
743 sxtab r0, r1, r2, ROR #24 :: rd 0x3141594e rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000…
744 sxtab r0, r1, r2, ROR #16 :: rd 0x3141593f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000…
745 sxtab r0, r1, r2, ROR #8 :: rd 0x3141594f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 …
746 sxtab r0, r1, r2, ROR #0 :: rd 0x31415940 rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 …
747 sxtab r0, r1, r2, ROR #24 :: rd 0x3141594e rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000…
748 sxtab r0, r1, r2, ROR #16 :: rd 0x3141593f rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000…
749 sxtab r0, r1, r2, ROR #8 :: rd 0x3141594f rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000 …
750 sxtab r0, r1, r2, ROR #0 :: rd 0x314158c0 rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000 …
[all …]
/external/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64AddressingModes.h37 ROR, enumerator
58 case AArch64_AM::ROR: return "ror"; in getShiftExtendName()
79 case 3: return AArch64_AM::ROR; in getShiftType()
107 case AArch64_AM::ROR: STEnc = 3; break; in getShifterImm()
/external/v8/test/cctest/
Dtest-disasm-arm.cc158 COMPARE(sbc(r7, r1, Operand(ip, ROR, 1), LeaveCC, hi), in TEST()
160 COMPARE(sbc(r7, r9, Operand(ip, ROR, 4)), in TEST()
164 COMPARE(sbc(r7, ip, Operand(ip, ROR, 31), SetCC, hi), in TEST()
185 COMPARE(teq(r7, Operand(r5, ROR, r0), lt), in TEST()
187 COMPARE(teq(r7, Operand(r6, ROR, lr)), in TEST()
191 COMPARE(teq(r7, Operand(r8, ROR, r1)), in TEST()
205 COMPARE(cmn(r1, Operand(r6, ROR, 1)), in TEST()
Dtest-disasm-arm64.cc716 COMPARE(and_(w12, w13, Operand(w14, ROR, 4)), "and w12, w13, w14, ror #4"); in TEST_()
722 COMPARE(bic(w27, w28, Operand(w29, ROR, 8)), "bic w27, w28, w29, ror #8"); in TEST_()
728 COMPARE(orr(w12, w13, Operand(w14, ROR, 12)), "orr w12, w13, w14, ror #12"); in TEST_()
734 COMPARE(orn(w27, w28, Operand(w29, ROR, 16)), "orn w27, w28, w29, ror #16"); in TEST_()
740 COMPARE(eor(w12, w13, Operand(w14, ROR, 20)), "eor w12, w13, w14, ror #20"); in TEST_()
746 COMPARE(eon(w27, w28, Operand(w29, ROR, 24)), "eon w27, w28, w29, ror #24"); in TEST_()
752 COMPARE(ands(w12, w13, Operand(w14, ROR, 4)), "ands w12, w13, w14, ror #4"); in TEST_()
758 COMPARE(bics(w27, w28, Operand(w29, ROR, 8)), "bics w27, w28, w29, ror #8"); in TEST_()
761 COMPARE(tst(w2, Operand(w3, ROR, 10)), "tst w2, w3, ror #10"); in TEST_()
763 COMPARE(tst(x2, Operand(x3, ROR, 42)), "tst x2, x3, ror #42"); in TEST_()
Dtest-assembler-arm64.cc305 __ Mvn(w8, Operand(w0, ROR, 13)); in TEST()
306 __ Mvn(x9, Operand(x1, ROR, 14)); in TEST()
378 __ Mov(w21, Operand(w11, ROR, 13)); in TEST()
379 __ Mov(x22, Operand(x12, ROR, 14)); in TEST()
534 __ Orr(w8, w0, Operand(w1, ROR, 12)); in TEST()
535 __ Orr(x9, x0, Operand(x1, ROR, 12)); in TEST()
631 __ Orn(w8, w0, Operand(w1, ROR, 16)); in TEST()
632 __ Orn(x9, x0, Operand(x1, ROR, 16)); in TEST()
700 __ And(w8, w0, Operand(w1, ROR, 28)); in TEST()
701 __ And(x9, x0, Operand(x1, ROR, 28)); in TEST()
[all …]
/external/v8/src/parsing/
Dtoken.h79 T(ROR, "rotate right", 11) /* only used by Crankshaft */ \
225 return BIT_OR <= op && op <= ROR; in IsTruncatingBinaryOp()
/external/v8/src/arm/
Dconstants-arm.h244 ROR = 3 << 5, // Rotate right. enumerator
Dsimulator-arm.cc1406 if ((shift == ROR) && (shift_amount == 0)) { in GetShiftRm()
1455 case ROR: { in GetShiftRm()
1534 case ROR: { in GetShiftRm()
Ddisasm-arm.cc203 if ((shift == ROR) && (shift_amount == 0)) { in PrintShiftRm()
/external/llvm/test/MC/Disassembler/ARM/
Dthumb1.txt354 # ROR
/external/valgrind/VEX/priv/
Dguest_arm64_toIR.c3516 #define ROR(_v128,_nbytes) \ macro
3629 assign(*i1, ILO64x2( ROR(EX(u0),8), EX(u2) )); in math_INTERLEAVE3_128()
3653 AND( IHI32x4(ROR(EX(p1),4), EX(p2)), EX(c0011) ) )); in math_INTERLEAVE3_128()
3658 AND( ILO32x4(ROR(EX(p0),8),EX(p0)), EX(c0011) ) )); in math_INTERLEAVE3_128()
3694 AND( ILO16x8( ROR(EX(p2),2), ROL(EX(p1),2) ), EX(c0001) ) in math_INTERLEAVE3_128()
3697 OR4( AND( IHI16x8( ROL(EX(p1),4), ROR(EX(p2),2) ), EX(c1000) ), in math_INTERLEAVE3_128()
3700 AND( IHI16x8( ROR(EX(p0),6), ROL(EX(p1),4) ), EX(c0001) ) in math_INTERLEAVE3_128()
3703 OR4( AND( IHI16x8( ROR(EX(p1),2), ROL(EX(p0),2) ), EX(c1000) ), in math_INTERLEAVE3_128()
3736 ILO8x16( ROR(EX(_srcVec1),(_srcShift1)), \ in math_INTERLEAVE3_128()
3737 ROR(EX(_srcVec2),(_srcShift2)) ) ) in math_INTERLEAVE3_128()
[all …]
/external/vixl/src/vixl/a64/
Dmacro-assembler-a64.cc1395 (operand.IsShiftedRegister() && (operand.shift() == ROR))) { in AddSubMacro()
1473 (operand.IsShiftedRegister() && (operand.shift() == ROR))) { in AddSubWithCarryMacro()
1481 VIXL_ASSERT(operand.shift() != ROR); in AddSubWithCarryMacro()
/external/vixl/test/
Dtest-assembler-a64.cc298 __ Mvn(w8, Operand(w0, ROR, 13)); in TEST()
299 __ Mvn(x9, Operand(x1, ROR, 14)); in TEST()
471 __ Mov(w21, Operand(w11, ROR, 13)); in TEST()
472 __ Mov(x22, Operand(x12, ROR, 14)); in TEST()
529 __ Orr(w8, w0, Operand(w1, ROR, 12)); in TEST()
530 __ Orr(x9, x0, Operand(x1, ROR, 12)); in TEST()
623 __ Orn(w8, w0, Operand(w1, ROR, 16)); in TEST()
624 __ Orn(x9, x0, Operand(x1, ROR, 16)); in TEST()
690 __ And(w8, w0, Operand(w1, ROR, 28)); in TEST()
691 __ And(x9, x0, Operand(x1, ROR, 28)); in TEST()
[all …]
Dtest-disasm-a64.cc814 COMPARE(and_(w12, w13, Operand(w14, ROR, 4)), "and w12, w13, w14, ror #4"); in TEST()
820 COMPARE(bic(w27, w28, Operand(w29, ROR, 8)), "bic w27, w28, w29, ror #8"); in TEST()
826 COMPARE(orr(w12, w13, Operand(w14, ROR, 12)), "orr w12, w13, w14, ror #12"); in TEST()
832 COMPARE(orn(w27, w28, Operand(w29, ROR, 16)), "orn w27, w28, w29, ror #16"); in TEST()
838 COMPARE(eor(w12, w13, Operand(w14, ROR, 20)), "eor w12, w13, w14, ror #20"); in TEST()
844 COMPARE(eon(w27, w28, Operand(w29, ROR, 24)), "eon w27, w28, w29, ror #24"); in TEST()
850 COMPARE(ands(w12, w13, Operand(w14, ROR, 4)), "ands w12, w13, w14, ror #4"); in TEST()
856 COMPARE(bics(w27, w28, Operand(w29, ROR, 8)), "bics w27, w28, w29, ror #8"); in TEST()
859 COMPARE(tst(w2, Operand(w3, ROR, 10)), "tst w2, w3, ror #10"); in TEST()
861 COMPARE(tst(x2, Operand(x3, ROR, 42)), "tst x2, x3, ror #42"); in TEST()
/external/v8/src/compiler/arm/
Dcode-generator-arm.cc111 return Operand(InputRegister(index + 0), ROR, InputInt5(index + 1)); in InputOperand2()
113 return Operand(InputRegister(index + 0), ROR, InputRegister(index + 1)); in InputOperand2()
/external/llvm/test/MC/ARM/
Dbasic-thumb-instructions.s484 @ ROR
/external/v8/src/compiler/arm64/
Dcode-generator-arm64.cc95 return Operand(InputRegister32(index), ROR, InputInt5(index + 1)); in InputOperand2_32()
123 return Operand(InputRegister64(index), ROR, InputInt6(index + 1)); in InputOperand2_64()
/external/llvm/lib/Target/AArch64/Utils/
DAArch64BaseInfo.h503 ROR, enumerator
/external/llvm/lib/Target/AArch64/AsmParser/
DAArch64AsmParser.cpp994 ST == AArch64_AM::ASR || ST == AArch64_AM::ROR || in isShifter()
1063 ST == AArch64_AM::ASR || ST == AArch64_AM::ROR) && in isLogicalShifter()
2410 .Case("ror", AArch64_AM::ROR) in tryParseOptionalShiftExtend()
2431 ShOp == AArch64_AM::ASR || ShOp == AArch64_AM::ROR || in tryParseOptionalShiftExtend()
/external/v8/src/crankshaft/arm64/
Dlithium-arm64.cc348 case Token::ROR: return "ror-t"; in Mnemonic()
803 (op == Token::SHL) || (op == Token::SAR) || (op == Token::ROR) || in DoArithmeticT()
2220 return DoShift(Token::ROR, instr); in DoRor()
/external/v8/src/arm64/
Dconstants-arm64.h334 ROR = 0x3 enumerator
Dassembler-arm64-inl.h1109 DCHECK(shift == LSL || shift == LSR || shift == ASR || shift == ROR);

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