| /external/aac/libFDK/src/arm/ |
| D | dct_arm.cpp | 123 RSB r9, r9, #0 // accuX =-accu2*val_tw.l in dct_IV_func1()
133 RSB r9, r9, #0 // accuX =-accu4*val_tw.h in dct_IV_func1()
149 RSB r9, r9, #0 // accuX =-accu2*val_tw.l in dct_IV_func1()
159 RSB r9, r9, #0 // accuX =-accu4*val_tw.h in dct_IV_func1()
210 RSB accuX, accuX, #0 in dct_IV_func2()
220 RSB accuX, accuX, #0 in dct_IV_func2()
235 RSB accuX, accuX, #0 in dct_IV_func2()
245 RSB accuX, accuX, #0 in dct_IV_func2()
297 RSB r5, r5, #0 // accu2 = -accu2 in dst_IV_func1()
300 RSB r9, r9, #0 // accuX = -(-accu2)*val_tw.l in dst_IV_func1()
[all …]
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| /external/tremolo/Tremolo/ |
| D | bitwiseARM.s | 54 RSB r14,r12,#32 @ r14= 32-bitsLeftInWord
59 RSB r14,r14,#32 @ r14= 32-bitsLeftInWord
62 RSB r14,r14,r14,LSL r1
72 RSB r14,r12,#32 @ r14= 32-bitsLeftInWord
83 RSB r11,r11,r11,LSL r5 @ r11= mask
114 RSB r14,r14,r14,LSL r1
123 RSB r14,r14,r14,LSL r1
154 RSB r10,r10,#0 @ r10= bits to skip
195 RSB r10,r10,#32 @ r10= bits left in word
227 RSB r3,r3,#32 @ r3 = BitsInWord
[all …]
|
| D | mdctLARM.s | 126 RSB r12,r12,#0
127 RSB r5, r5, #0
128 RSB r6, r6, #0
129 RSB r7, r7, #0
166 RSB r5, r5, #0
328 RSB r6, r6, #0
348 RSB r6, r6, #0
382 RSB r8, r8, #0 @ r8 = -ro0
393 RSB r6, r6, #0 @ r6 = -ri0
488 RSB r11,r11,#0
[all …]
|
| D | mdctARM.s | 128 RSB r12,r12,#0
129 RSB r5, r5, #0
130 RSB r6, r6, #0
131 RSB r7, r7, #0
168 RSB r5, r5, #0
330 RSB r6, r6, #0
354 RSB r6, r6, #0
387 RSB r8,r8,#0 @ r8 = -ro0
404 RSB r6,r6,#0 @ r6 = -ri0
503 RSB r11,r11,#0
[all …]
|
| D | dpen.s | 96 RSB r1, r4, #0 @ r1 = i-read = 0-read
120 RSB r1, r4, #0 @ r1 = i = -read
152 RSB r1, r4, #0 @ r1 = i-read = 0-read
177 RSB r1, r4, #0 @ r1 = i = -read
211 RSB r1, r4, #0 @ r1 = i-read = 0-read
294 RSB r0, r0, r0, LSL r2 @ r0 = mask = (1<<s->q_bits)-1
323 RSB r0, r0, r0, LSL r1 @ r8 = mask = (1<<s->q_pack)-1
|
| /external/libhevc/decoder/arm/ |
| D | ihevcd_fmt_conv_420sp_to_420p.s | 128 RSB r6,r6,#16
182 RSB r6,r6,#16
|
| D | ihevcd_fmt_conv_420sp_to_420sp.s | 126 RSB r6,r6,#32
179 RSB r6,r6,#16
|
| /external/sonivox/arm-wt-22k/lib_src/ |
| D | ARM-E_filter_gnu.s | 79 RSB b1, b1, #0 @ b1 = -b1
80 RSB b2, b2, #0 @ b2 = -b2
|
| /external/v8/src/arm/ |
| D | constants-arm.h | 144 RSB = 3 << 21, // Reverse Subtract. enumerator
|
| D | disasm-arm.cc | 868 case RSB: { in DecodeType01()
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| D | simulator-arm.cc | 2382 case RSB: { in DecodeType01()
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| D | assembler-arm.cc | 1439 addrmod1(cond | RSB | s, src1, dst, src2); in rsb()
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| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb1.txt | 361 # RSB
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| D | thumb2.txt | 1545 # RSB (immediate)
1557 # RSB (register)
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| D | basic-arm-instructions.txt | 1269 # RSB
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| /external/v8/src/arm64/ |
| D | constants-arm64.h | 782 V(LD, RSB, x, 0x00800000), \
785 V(LD, RSB, w, 0x00C00000), \
|
| /external/llvm/test/MC/ARM/ |
| D | basic-thumb-instructions.s | 492 @ RSB
|
| D | thumb2-narrow-dp.ll | 724 // RSB - only two register version available
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| D | basic-thumb2-instructions.s | 2033 @ RSB (immediate)
2055 @ RSB (register)
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| D | basic-arm-instructions.s | 1937 @ RSB
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| D | v8_IT_manual.s | 247 @ RSB imm, encoding T1
251 @ RSB imm, encoding T2 (32-bit)
|
| /external/vixl/src/vixl/a64/ |
| D | constants-a64.h | 841 V(LD, RSB, x, 0x00800000), \
844 V(LD, RSB, w, 0x00C00000), \
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMScheduleSwift.td | 127 // ADC,ADD,NEG,RSB,RSC,SBC,SUB,ADR
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| D | ARMScheduleA9.td | 2276 def :ItinRW<[WriteALUsi, ReadDefault, A9ReadALU], [IIC_iALUsir]>; // RSB
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| D | ARMInstrThumb2.td | 2059 // RSB
4576 // Alias for RSB without the ".w" optional width specifier, and with optional
|