| /external/llvm/lib/Target/AMDGPU/ |
| D | R600OptimizeVectorRegisters.cpp | 80 bool operator==(const RegSeqInfo &RSI) const { in operator ==()
81 return RSI.Instr == Instr; in operator ==()
95 bool tryMergeUsingCommonSlot(RegSeqInfo &RSI, RegSeqInfo &CompatibleRSI,
97 bool tryMergeUsingFreeSlot(RegSeqInfo &RSI, RegSeqInfo &CompatibleRSI,
103 void trackRSI(const RegSeqInfo &RSI);
179 RegSeqInfo *RSI, const RegSeqInfo *BaseRSI, in RebuildVector() argument
181 unsigned Reg = RSI->Instr->getOperand(0).getReg(); in RebuildVector()
182 MachineBasicBlock::iterator Pos = RSI->Instr; in RebuildVector()
189 for (DenseMap<unsigned, unsigned>::iterator It = RSI->RegToChan.begin(), in RebuildVector()
190 E = RSI->RegToChan.end(); It != E; ++It) { in RebuildVector()
[all …]
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| /external/libunwind/src/x86_64/ |
| D | init.h | 53 c->dwarf.loc[RSI] = REG_INIT_LOC(c, rsi, RSI); in common_init()
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| D | unwind_i.h | 43 #define RSI 4 macro
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| D | Gregs.c | 111 case UNW_X86_64_RSI: loc = c->dwarf.loc[RSI]; break; in tdep_access_reg()
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| D | Gos-freebsd.c | 115 c->dwarf.loc[RSI] = DWARF_LOC (ucontext + UC_MCONTEXT_GREGS_RSI, 0); in unw_handle_signal_frame()
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| /external/strace/linux/x86_64/ |
| D | userent.h | 14 XLAT(8*RSI),
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| /external/llvm/lib/Target/X86/ |
| D | X86CallingConv.td | 212 CCIfType<[i64], CCAssignToReg<[RBX, RBP, RDI, RSI, RDX, RCX, R8, R9,
278 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
340 RDI, RSI, RDX, RCX, R8, R9,
429 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>,
442 CCIfType<[i64], CCAssignToReg<[R15, RBP, RSI, RDX, RCX, R8]>>,
718 CCIfType<[i64], CCIfSubtarget<"is64Bit()", CCAssignToReg<[RDI, RSI, RDX, RCX]>>>,
807 def CSR_Win64 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, R13, R14, R15,
813 def CSR_64_TLS_Darwin : CalleeSavedRegs<(add CSR_64, RCX, RDX, RSI,
817 def CSR_64_RT_MostRegs : CalleeSavedRegs<(add CSR_64, RAX, RCX, RDX, RSI, RDI,
826 def CSR_64_MostRegs : CalleeSavedRegs<(add RBX, RCX, RDX, RSI, RDI, R8, R9, R10,
[all …]
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| D | X86RegisterInfo.cpp | 642 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: in getX86SubSuperRegisterOrZero()
670 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: in getX86SubSuperRegisterOrZero()
707 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: in getX86SubSuperRegisterOrZero()
743 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: in getX86SubSuperRegisterOrZero()
779 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: in getX86SubSuperRegisterOrZero()
780 return X86::RSI; in getX86SubSuperRegisterOrZero()
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| D | X86SelectionDAGInfo.cpp | 225 const unsigned ClobberSet[] = {X86::RCX, X86::RSI, X86::RDI, in EmitTargetCodeForMemcpy()
254 Chain = DAG.getCopyToReg(Chain, dl, Subtarget.is64Bit() ? X86::RSI : X86::ESI, in EmitTargetCodeForMemcpy()
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| D | X86InstrSystem.td | 538 let Defs = [RSI, RDI], Uses = [RBX, RDX, RSI, RDI] in {
546 let Defs = [RAX, RSI, RDI], Uses = [RAX, RSI, RDI] in {
550 let Defs = [RAX, RDX, RSI], Uses = [RAX, RSI] in
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| D | X86RegisterInfo.td | 133 def RSI : X86Reg<"rsi", 6, [ESI]>, DwarfRegNum<[4, -2, -2]>;
349 (add RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
375 def GR64_TC : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RSI, RDI,
396 (add RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP)>;
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| /external/kernel-headers/original/uapi/asm-x86/asm/ |
| D | ptrace-abi.h | 46 #define RSI 104 macro
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| /external/llvm/utils/TableGen/ |
| D | CodeGenSchedule.cpp | 1026 RSI = PTI->ReadSequences.begin(), RSE = PTI->ReadSequences.end(); in hasVariant() local
1027 RSI != RSE; ++RSI) { in hasVariant()
1029 RI = RSI->begin(), RE = RSI->end(); RI != RE; ++RI) { in hasVariant()
1263 RSI = Trans.ReadSequences.begin(), RSE = Trans.ReadSequences.end(); in substituteVariants() local
1264 RSI != RSE; ++RSI) { in substituteVariants()
1270 substituteVariantOperand(*RSI, /*IsRead=*/true, StartIdx); in substituteVariants()
1292 RSI = I->ReadSequences.begin(), RSE = I->ReadSequences.end(); in inferFromTransitions() local
1293 RSI != RSE; ++RSI) { in inferFromTransitions()
1296 SchedModels.findOrInsertRW(*RSI, /*IsRead=*/true)); in inferFromTransitions()
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| /external/valgrind/coregrind/m_sigframe/ |
| D | sigframe-amd64-darwin.c | 102 SC2(__rsi,RSI); in synthesize_ucontext()
130 SC2(RSI,__rsi); in restore_from_ucontext()
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| D | sigframe-amd64-linux.c | 354 SC2(rsi,RSI); in synth_ucontext()
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| /external/llvm/test/tools/llvm-objdump/ |
| D | win64-unwind-data.test | 22 OBJ-NEXT: 0x09: UOP_SaveNonVol RSI [0x0010]
71 EXE-NEXT: 0x09: UOP_SaveNonVol RSI [0x0010]
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| /external/lzma/Asm/x86/ |
| D | 7zAsm.asm | 72 r6 equ RSI
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| /external/llvm/lib/Target/X86/Disassembler/ |
| D | X86DisassemblerDecoder.h | 177 ENTRY(RSI) \
195 ENTRY(RSI) \
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| /external/google-breakpad/src/common/android/ |
| D | breakpad_getcontext_unittest.cc | 130 CHECK_REG(RSI); in TEST()
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| /external/llvm/lib/Target/X86/AsmParser/ |
| D | X86Operand.h | 292 (getMemBaseReg() == X86::RSI || getMemBaseReg() == X86::ESI || in isSrcIdx()
398 case X86::RSI: return X86::ESI; in getGR32FromGR64()
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| /external/llvm/test/CodeGen/X86/ |
| D | ghc-cc64.ll | 10 @r3 = external global i64 ; assigned to register: RSI
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| /external/llvm/include/llvm/DebugInfo/PDB/ |
| D | PDBTypes.h | 408 RSI = 332, enumerator
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| /external/llvm/test/DebugInfo/X86/ |
| D | live-debug-values.ll | 34 ; CHECK-NEXT: #DEBUG_VALUE: main:argv <- %RSI
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| /external/clang/lib/Sema/ |
| D | SemaStmt.cpp | 3897 CapturedRegionScopeInfo *RSI = getCurCapturedRegion(); in ActOnCapturedRegionError() local
3898 RecordDecl *Record = RSI->TheRecordDecl; in ActOnCapturedRegionError()
3910 CapturedRegionScopeInfo *RSI = getCurCapturedRegion(); in ActOnCapturedRegionEnd() local
3914 buildCapturedStmtCaptureList(Captures, CaptureInits, RSI->Captures); in ActOnCapturedRegionEnd()
3916 CapturedDecl *CD = RSI->TheCapturedDecl; in ActOnCapturedRegionEnd()
3917 RecordDecl *RD = RSI->TheRecordDecl; in ActOnCapturedRegionEnd()
3920 RSI->CapRegionKind, Captures, in ActOnCapturedRegionEnd()
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| /external/llvm/lib/DebugInfo/PDB/ |
| D | PDBExtras.cpp | 131 CASE_OUTPUT_ENUM_CLASS_NAME(PDB_RegisterId, RSI, OS) in operator <<()
|