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Searched refs:SETULT (Results 1 – 25 of 36) sorted by relevance

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/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h855 SETULT, // 1 1 0 0 True if unordered or less than enumerator
881 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; in isUnsignedIntSetCC()
/external/llvm/lib/CodeGen/SelectionDAG/
DTargetLowering.cpp189 case ISD::SETULT: in softenSetCCOperands()
1327 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){ in SimplifySetCC()
1331 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; in SimplifySetCC()
1463 case ISD::SETULT: in SimplifySetCC()
1485 case ISD::SETULT: in SimplifySetCC()
1650 ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT; in SimplifySetCC()
1661 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) in SimplifySetCC()
1674 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) in SimplifySetCC()
1678 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) in SimplifySetCC()
1699 if (Cond == ISD::SETULT && in SimplifySetCC()
[all …]
DLegalizeIntegerTypes.cpp968 case ISD::SETULT: in PromoteSetCCOperands()
1616 Amt, NVBitsNode, ISD::SETULT); in ExpandShiftWithUnknownAmountBit()
1747 ISD::SETULT); in ExpandIntRes_ADDSUB()
1752 ISD::SETULT); in ExpandIntRes_ADDSUB()
1761 LoOps[0], LoOps[1], ISD::SETULT); in ExpandIntRes_ADDSUB()
2445 ISD::SETULT : ISD::SETUGT); in ExpandIntRes_UADDSUBO()
2743 case ISD::SETULT: LowCC = ISD::SETULT; break; in IntegerExpandSetCCOperands()
2785 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { in IntegerExpandSetCCOperands()
2812 case ISD::SETUGT: CCCode = ISD::SETULT; FlipOperands = true; break; in IntegerExpandSetCCOperands()
DSelectionDAGDumper.cpp342 case ISD::SETULT: return "setult"; in getOperationName()
/external/llvm/lib/CodeGen/
DAnalysis.cpp177 case FCmpInst::FCMP_ULT: return ISD::SETULT; in getFCmpCondCode()
189 case ISD::SETOLT: case ISD::SETULT: return ISD::SETLT; in getFCmpCodeWithoutNaN()
209 case ICmpInst::ICMP_ULT: return ISD::SETULT; in getICmpCondCode()
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrInteger.td46 defm LT_U : ComparisonInt<SETULT, "lt_u">;
DWebAssemblyISelLowering.cpp132 ISD::SETULT, ISD::SETULE, ISD::SETUGT, ISD::SETUGE}) in WebAssemblyTargetLowering()
/external/mesa3d/src/gallium/drivers/radeon/
DAMDGPUInstructions.td66 case ISD::SETOLT: case ISD::SETULT:
DAMDILISelLowering.cpp135 setOperationAction(ISD::SETULT, VT, Expand); in InitAMDILLowering()
DR600Instructions.td1205 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETULT),
/external/llvm/lib/Target/Hexagon/
DHexagonSelectCCInfo.td37 IntRegs:$fval, SETULT)),
/external/llvm/lib/Target/AMDGPU/
DR600ISelLowering.cpp56 setCondCodeAction(ISD::SETULT, MVT::f32, Expand); in R600TargetLowering()
62 setCondCodeAction(ISD::SETULT, MVT::i32, Expand); in R600TargetLowering()
1017 Hi = DAG.getSelectCC(DL, Shift, Width, HiSmall, HiBig, ISD::SETULT); in LowerSHLParts()
1018 Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT); in LowerSHLParts()
1055 Hi = DAG.getSelectCC(DL, Shift, Width, HiSmall, HiBig, ISD::SETULT); in LowerSRXParts()
1056 Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT); in LowerSRXParts()
DAMDGPUInstructions.td111 def COND_ULT : PatLeaf <(cond), [{return N->get() == ISD::SETULT;}]>;
/external/llvm/lib/Target/PowerPC/
DPPCInstrQPX.td1013 def : Pat<(setcc v4f64:$FRA, v4f64:$FRB, SETULT),
1060 def : Pat<(setcc v4f32:$FRA, v4f32:$FRB, SETULT),
1119 def : Pat<(v4f64 (selectcc i1:$lhs, i1:$rhs, v4f64:$tval, v4f64:$fval, SETULT)),
1140 def : Pat<(v4f32 (selectcc i1:$lhs, i1:$rhs, v4f32:$tval, v4f32:$fval, SETULT)),
1161 def : Pat<(v4i1 (selectcc i1:$lhs, i1:$rhs, v4i1:$tval, v4i1:$fval, SETULT)),
DPPCISelDAGToDAG.cpp2115 case ISD::SETULT: return PPC::PRED_LT; in getPredicateForSetCC()
2147 case ISD::SETULT: return 0; in getCRIdxForSetCC()
2168 case ISD::SETUGT: CC = ISD::SETULT; Swap = true; break; in getVCmpInst()
2176 case ISD::SETULT: CC = ISD::SETOGE; Negate = true; break; in getVCmpInst()
2212 case ISD::SETULT: CC = ISD::SETUGT; Swap = true; break; in getVCmpInst()
3160 if (Op0.getOpcode() == ISD::XOR && CC == ISD::SETULT && in combineToCMPB()
DPPCInstrInfo.td2861 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)),
2924 // SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for
3064 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)),
3109 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETULT)),
3132 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULT)),
3177 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETULT)),
3272 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULT)),
3303 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULT)),
3324 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULT)),
3345 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)),
[all …]
DPPCInstrVSX.td952 def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETULT)),
973 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULT)),
1072 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)),
/external/llvm/lib/Target/BPF/
DBPFISelLowering.cpp468 case ISD::SETULT: in NegateCC()
/external/llvm/lib/Target/Mips/
DMipsSEISelLowering.cpp963 case ISD::SETULT: in isLegalDSPCondCode()
1010 else if (CondCode == ISD::SETULT || CondCode == ISD::SETULE) in performVSELECTCombine()
1740 Op->getOperand(2), ISD::SETULT); in lowerINTRINSIC_WO_CHAIN()
1746 lowerMSASplatImm(Op, 2, DAG), ISD::SETULT); in lowerINTRINSIC_WO_CHAIN()
1830 Op->getOperand(2), ISD::SETULT); in lowerINTRINSIC_WO_CHAIN()
DMipsMSAInstrInfo.td183 def vfsetult_v4f32 : vfsetcc_type<v4i32, v4f32, SETULT>;
184 def vfsetult_v2f64 : vfsetcc_type<v2i64, v2f64, SETULT>;
211 def vsetult_v16i8 : vsetcc_type<v16i8, SETULT>;
212 def vsetult_v8i16 : vsetcc_type<v8i16, SETULT>;
213 def vsetult_v4i32 : vsetcc_type<v4i32, SETULT>;
214 def vsetult_v2i64 : vsetcc_type<v2i64, SETULT>;
DMipsDSPInstrInfo.td1396 def : DSPSetCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>;
1409 def : DSPSelectCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>;
/external/llvm/include/llvm/Target/
DTargetSelectionDAG.td583 def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode;
971 (setcc node:$lhs, node:$rhs, SETULT)>;
/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp1070 case ISD::SETULT: in changeIntCCToAArch64CC()
1124 case ISD::SETULT: in changeFPCCToAArch64CC()
1159 case ISD::SETULT: in changeVectorFPCCToAArch64CC()
1456 case ISD::SETULT: in getAArch64Cmp()
1461 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT; in getAArch64Cmp()
1483 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; in getAArch64Cmp()
8981 (Op == ISD::UMIN && CC != ISD::SETULT && CC != ISD::SETULE) || in performAcrossLaneMinMaxReductionCombine()
8986 CC != ISD::SETULT && CC != ISD::SETULE && CC != ISD::SETLT && in performAcrossLaneMinMaxReductionCombine()
/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp1323 case ISD::SETULT: return ARMCC::LO; in IntCCToARMCC()
1349 case ISD::SETULT: CondCode = ARMCC::LT; break; in FPCCToARMCC()
3307 case ISD::SETULT: in getARMCmp()
3310 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT; in getARMCmp()
3324 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; in getARMCmp()
3529 CC == ISD::SETULT) in checkVSELConstraints()
3535 CC == ISD::SETULT) in checkVSELConstraints()
3546 if (CC == ISD::SETULE || CC == ISD::SETULT || CC == ISD::SETUGE || in checkVSELConstraints()
4645 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break; in LowerVSETCC()
4675 case ISD::SETULT: Swap = true; in LowerVSETCC()
/external/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp849 case ISD::SETULT: in EmitCMP()

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