/external/llvm/lib/Target/ARM/InstPrinter/ |
D | ARMInstPrinter.h | 30 const MCSubtargetInfo &STI) override; 34 void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI, 38 void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, 42 const MCSubtargetInfo &STI, raw_ostream &O); 44 const MCSubtargetInfo &STI, raw_ostream &O); 47 const MCSubtargetInfo &STI, raw_ostream &O); 49 const MCSubtargetInfo &STI, raw_ostream &O); 51 const MCSubtargetInfo &STI, raw_ostream &O); 53 const MCSubtargetInfo &STI, raw_ostream &O); 55 const MCSubtargetInfo &STI, raw_ostream &O); [all …]
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D | ARMInstPrinter.cpp | 70 StringRef Annot, const MCSubtargetInfo &STI) { in printInst() argument 96 if (STI.getFeatureBits()[ARM::HasV8Ops]) { in printInst() 102 printInstruction(MI, STI, O); in printInst() 106 printPredicateOperand(MI, 1, STI, O); in printInst() 121 printSBitModifierOperand(MI, 6, STI, O); in printInst() 122 printPredicateOperand(MI, 4, STI, O); in printInst() 143 printSBitModifierOperand(MI, 5, STI, O); in printInst() 144 printPredicateOperand(MI, 3, STI, O); in printInst() 168 printPredicateOperand(MI, 2, STI, O); in printInst() 172 printRegisterList(MI, 4, STI, O); in printInst() [all …]
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/external/llvm/lib/Target/Mips/MCTargetDesc/ |
D | MipsMCCodeEmitter.h | 40 bool isMicroMips(const MCSubtargetInfo &STI) const; 41 bool isMips32r6(const MCSubtargetInfo &STI) const; 51 void EmitInstruction(uint64_t Val, unsigned Size, const MCSubtargetInfo &STI, 56 const MCSubtargetInfo &STI) const override; 62 const MCSubtargetInfo &STI) const; 69 const MCSubtargetInfo &STI) const; 76 const MCSubtargetInfo &STI) const; 82 const MCSubtargetInfo &STI) const; 86 const MCSubtargetInfo &STI) const; 90 const MCSubtargetInfo &STI) const; [all …]
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D | MipsMCCodeEmitter.cpp | 115 bool MipsMCCodeEmitter::isMicroMips(const MCSubtargetInfo &STI) const { in isMicroMips() 116 return STI.getFeatureBits()[Mips::FeatureMicroMips]; in isMicroMips() 119 bool MipsMCCodeEmitter::isMips32r6(const MCSubtargetInfo &STI) const { in isMips32r6() 120 return STI.getFeatureBits()[Mips::FeatureMips32r6]; in isMips32r6() 128 const MCSubtargetInfo &STI, in EmitInstruction() argument 134 if (IsLittleEndian && Size == 4 && isMicroMips(STI)) { in EmitInstruction() 135 EmitInstruction(Val >> 16, 2, STI, OS); in EmitInstruction() 136 EmitInstruction(Val, 2, STI, OS); in EmitInstruction() 150 const MCSubtargetInfo &STI) const in encodeInstruction() 173 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); in encodeInstruction() [all …]
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D | MipsNaClELFStreamer.cpp | 94 const MCSubtargetInfo &STI) { in emitMask() argument 100 MipsELFStreamer::EmitInstruction(MaskInst, STI); in emitMask() 105 void sandboxIndirectJump(const MCInst &MI, const MCSubtargetInfo &STI) { in sandboxIndirectJump() argument 109 emitMask(AddrReg, IndirectBranchMaskReg, STI); in sandboxIndirectJump() 110 MipsELFStreamer::EmitInstruction(MI, STI); in sandboxIndirectJump() 117 const MCSubtargetInfo &STI, bool MaskBefore, in sandboxLoadStoreStackChange() argument 123 emitMask(BaseReg, LoadStoreStackMaskReg, STI); in sandboxLoadStoreStackChange() 125 MipsELFStreamer::EmitInstruction(MI, STI); in sandboxLoadStoreStackChange() 130 emitMask(SPReg, LoadStoreStackMaskReg, STI); in sandboxLoadStoreStackChange() 139 const MCSubtargetInfo &STI) override { in EmitInstruction() argument [all …]
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/external/llvm/lib/Target/AArch64/InstPrinter/ |
D | AArch64InstPrinter.h | 32 const MCSubtargetInfo &STI) override; 36 virtual void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI, 38 virtual bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI, 42 const MCSubtargetInfo &STI, 51 bool printSysAlias(const MCInst *MI, const MCSubtargetInfo &STI, 54 void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, 56 void printHexImm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, 62 const MCSubtargetInfo &STI, raw_ostream &O) { in printPostIncOperand() argument 67 const MCSubtargetInfo &STI, raw_ostream &O); 69 const MCSubtargetInfo &STI, raw_ostream &O); [all …]
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D | AArch64InstPrinter.cpp | 52 const MCSubtargetInfo &STI) { in printInst() argument 58 if (printSysAlias(MI, STI, O)) { in printInst() 221 if (!printAliasInstr(MI, STI, O)) in printInst() 222 printInstruction(MI, STI, O); in printInst() 626 const MCSubtargetInfo &STI) { in printInst() argument 636 printVectorList(MI, ListOpNum, STI, O, ""); in printInst() 650 printVectorList(MI, OpNum++, STI, O, ""); in printInst() 674 AArch64InstPrinter::printInst(MI, O, Annot, STI); in printInst() 678 const MCSubtargetInfo &STI, in printSysAlias() argument 736 (STI.getFeatureBits()[AArch64::HasV8_2aOps])) in printSysAlias() [all …]
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/external/llvm/lib/Target/ARM/MCTargetDesc/ |
D | ARMMCCodeEmitter.cpp | 53 bool isThumb(const MCSubtargetInfo &STI) const { in isThumb() 54 return STI.getFeatureBits()[ARM::ModeThumb]; in isThumb() 56 bool isThumb2(const MCSubtargetInfo &STI) const { in isThumb2() 57 return isThumb(STI) && STI.getFeatureBits()[ARM::FeatureThumb2]; in isThumb2() 59 bool isTargetMachO(const MCSubtargetInfo &STI) const { in isTargetMachO() 60 const Triple &TT = STI.getTargetTriple(); in isTargetMachO() 70 const MCSubtargetInfo &STI) const; 76 const MCSubtargetInfo &STI) const; 83 const MCSubtargetInfo &STI) const; 88 const MCSubtargetInfo &STI) const; [all …]
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/external/llvm/lib/Target/SystemZ/MCTargetDesc/ |
D | SystemZMCCodeEmitter.cpp | 42 const MCSubtargetInfo &STI) const override; 48 const MCSubtargetInfo &STI) const; 54 const MCSubtargetInfo &STI) const; 62 const MCSubtargetInfo &STI) const; 65 const MCSubtargetInfo &STI) const; 68 const MCSubtargetInfo &STI) const; 71 const MCSubtargetInfo &STI) const; 74 const MCSubtargetInfo &STI) const; 77 const MCSubtargetInfo &STI) const; 91 const MCSubtargetInfo &STI) const { in getPC16DBLEncoding() [all …]
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/external/llvm/lib/Target/AArch64/MCTargetDesc/ |
D | AArch64MCCodeEmitter.cpp | 50 const MCSubtargetInfo &STI) const; 56 const MCSubtargetInfo &STI) const; 64 const MCSubtargetInfo &STI) const; 70 const MCSubtargetInfo &STI) const; 76 const MCSubtargetInfo &STI) const; 82 const MCSubtargetInfo &STI) const; 88 const MCSubtargetInfo &STI) const; 95 const MCSubtargetInfo &STI) const; 101 const MCSubtargetInfo &STI) const; 107 const MCSubtargetInfo &STI) const; [all …]
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/external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
D | PPCMCCodeEmitter.cpp | 53 const MCSubtargetInfo &STI) const; 56 const MCSubtargetInfo &STI) const; 59 const MCSubtargetInfo &STI) const; 62 const MCSubtargetInfo &STI) const; 65 const MCSubtargetInfo &STI) const; 68 const MCSubtargetInfo &STI) const; 71 const MCSubtargetInfo &STI) const; 74 const MCSubtargetInfo &STI) const; 77 const MCSubtargetInfo &STI) const; 80 const MCSubtargetInfo &STI) const; [all …]
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/external/llvm/lib/Target/Sparc/InstPrinter/ |
D | SparcInstPrinter.cpp | 37 bool SparcInstPrinter::isV9(const MCSubtargetInfo &STI) const { in isV9() 38 return (STI.getFeatureBits()[Sparc::FeatureV9]) != 0; in isV9() 47 StringRef Annot, const MCSubtargetInfo &STI) { in printInst() argument 48 if (!printAliasInstr(MI, STI, O) && !printSparcAliasInstr(MI, STI, O)) in printInst() 49 printInstruction(MI, STI, O); in printInst() 54 const MCSubtargetInfo &STI, in printSparcAliasInstr() argument 75 O << "\tjmp "; printMemOperand(MI, 1, STI, O); in printSparcAliasInstr() 78 O << "\tcall "; printMemOperand(MI, 1, STI, O); in printSparcAliasInstr() 84 if (isV9(STI) in printSparcAliasInstr() 99 printOperand(MI, 1, STI, O); in printSparcAliasInstr() [all …]
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D | SparcInstPrinter.h | 32 const MCSubtargetInfo &STI) override; 33 bool printSparcAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI, 35 bool isV9(const MCSubtargetInfo &STI) const; 38 void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI, 40 bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI, 44 const MCSubtargetInfo &STI, raw_ostream &O); 47 void printOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI, 49 void printMemOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI, 51 void printCCOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI, 53 bool printGetPCX(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
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/external/llvm/lib/Target/Sparc/MCTargetDesc/ |
D | SparcMCCodeEmitter.cpp | 46 const MCSubtargetInfo &STI) const override; 52 const MCSubtargetInfo &STI) const; 58 const MCSubtargetInfo &STI) const; 62 const MCSubtargetInfo &STI) const; 65 const MCSubtargetInfo &STI) const; 68 const MCSubtargetInfo &STI) const; 71 const MCSubtargetInfo &STI) const; 84 const MCSubtargetInfo &STI) const { in encodeInstruction() 85 unsigned Bits = getBinaryCodeForInstr(MI, Fixups, STI); in encodeInstruction() 105 uint64_t op = getMachineOpValue(MI, MO, Fixups, STI); in encodeInstruction() [all …]
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/external/llvm/lib/Target/AMDGPU/Utils/ |
D | AMDGPUBaseInfo.cpp | 125 bool isSI(const MCSubtargetInfo &STI) { in isSI() argument 126 return STI.getFeatureBits()[AMDGPU::FeatureSouthernIslands]; in isSI() 129 bool isCI(const MCSubtargetInfo &STI) { in isCI() argument 130 return STI.getFeatureBits()[AMDGPU::FeatureSeaIslands]; in isCI() 133 bool isVI(const MCSubtargetInfo &STI) { in isVI() argument 134 return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]; in isVI() 137 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI) { in getMCReg() argument 142 assert(!isSI(STI)); in getMCReg() 143 return isCI(STI) ? AMDGPU::FLAT_SCR_ci : AMDGPU::FLAT_SCR_vi; in getMCReg() 146 assert(!isSI(STI)); in getMCReg() [all …]
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/external/llvm/lib/Target/Sparc/ |
D | SparcAsmPrinter.cpp | 74 const MCSubtargetInfo &STI); 112 const MCSubtargetInfo &STI) in EmitCall() argument 117 OutStreamer.EmitInstruction(CallInst, STI); in EmitCall() 122 const MCSubtargetInfo &STI) in EmitSETHI() argument 128 OutStreamer.EmitInstruction(SETHIInst, STI); in EmitSETHI() 133 const MCSubtargetInfo &STI) in EmitBinary() argument 140 OutStreamer.EmitInstruction(Inst, STI); in EmitBinary() 145 const MCSubtargetInfo &STI) { in EmitOR() argument 146 EmitBinary(OutStreamer, SP::ORri, RS1, Imm, RD, STI); in EmitOR() 151 const MCSubtargetInfo &STI) { in EmitADD() argument [all …]
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/external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
D | HexagonMCShuffler.h | 30 HexagonMCShuffler(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, in HexagonMCShuffler() argument 32 : HexagonShuffler(MCII, STI) { in HexagonMCShuffler() 35 HexagonMCShuffler(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, 38 : HexagonShuffler(MCII, STI) { in HexagonShuffler() argument 56 bool HexagonMCShuffle(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, 58 bool HexagonMCShuffle(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, 60 unsigned HexagonMCShuffle(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
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D | HexagonMCShuffler.cpp | 40 append(MI, Extender, HexagonMCInstrInfo::getUnits(MCII, STI, *MI), in init() 55 append(AddMI, nullptr, HexagonMCInstrInfo::getUnits(MCII, STI, *AddMI), in init() 63 append(MI, Extender, HexagonMCInstrInfo::getUnits(MCII, STI, *MI), in init() 70 append(AddMI, nullptr, HexagonMCInstrInfo::getUnits(MCII, STI, *AddMI), in init() 101 bool llvm::HexagonMCShuffle(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, in HexagonMCShuffle() argument 103 HexagonMCShuffler MCS(MCII, STI, MCB); in HexagonMCShuffle() 151 llvm::HexagonMCShuffle(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, in HexagonMCShuffle() argument 179 HexagonMCShuffler MCS(MCII, STI, Attempt); // copy packet to the shuffler in HexagonMCShuffle() 195 HexagonMCShuffler MCS(MCII, STI, MCB); in HexagonMCShuffle() 205 bool llvm::HexagonMCShuffle(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, in HexagonMCShuffle() argument [all …]
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/external/llvm/lib/Target/Mips/ |
D | MipsAsmPrinter.cpp | 700 const MipsSubtarget STI(TT, CPU, FS, MTM.isLittleEndian(), MTM); in EmitStartOfAsmFile() local 702 bool IsABICalls = STI.isABICalls(); in EmitStartOfAsmFile() 723 STI.isNaN2008() ? getTargetStreamer().emitDirectiveNaN2008() in EmitStartOfAsmFile() 729 if (STI.isGP32bit()) in EmitStartOfAsmFile() 737 getTargetStreamer().updateABIInfo(STI); in EmitStartOfAsmFile() 742 if (ABI.IsO32() && (STI.isABI_FPXX() || STI.isFP64bit())) in EmitStartOfAsmFile() 748 if (ABI.IsO32() && (!STI.useOddSPReg() || STI.isABI_FPXX())) in EmitStartOfAsmFile() 774 void MipsAsmPrinter::EmitJal(const MCSubtargetInfo &STI, MCSymbol *Symbol) { in EmitJal() argument 779 OutStreamer->EmitInstruction(I, STI); in EmitJal() 782 void MipsAsmPrinter::EmitInstrReg(const MCSubtargetInfo &STI, unsigned Opcode, in EmitInstrReg() argument [all …]
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D | MipsSEFrameLowering.cpp | 373 MipsSEFrameLowering::MipsSEFrameLowering(const MipsSubtarget &STI) in MipsSEFrameLowering() argument 374 : MipsFrameLowering(STI, STI.stackAlignment()) {} in MipsSEFrameLowering() 383 *static_cast<const MipsSEInstrInfo *>(STI.getInstrInfo()); in emitPrologue() 385 *static_cast<const MipsRegisterInfo *>(STI.getRegisterInfo()); in emitPrologue() 389 MipsABIInfo ABI = STI.getABI(); in emitPrologue() 445 if (!STI.isLittle()) in emitPrologue() 461 if (!STI.isLittle()) in emitPrologue() 528 unsigned BP = STI.isABI_N64() ? Mips::S7_64 : Mips::S7; in emitPrologue() 549 if (!STI.hasMips32r2()) in emitInterruptPrologueStub() 558 if ((STI.getRelocationModel() != Reloc::Static)) in emitInterruptPrologueStub() [all …]
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/external/llvm/lib/Target/WebAssembly/MCTargetDesc/ |
D | WebAssemblyMCCodeEmitter.cpp | 44 const MCSubtargetInfo &STI) const; 50 const MCSubtargetInfo &STI) const; 54 const MCSubtargetInfo &STI) const; 58 const MCSubtargetInfo &STI) const override; 70 const MCSubtargetInfo &STI) const { in getMachineOpValue() 87 const MCSubtargetInfo &STI) const { in encodeInstruction() 95 const MCSubtargetInfo &STI) const { in getMemoryOpValue()
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/external/llvm/lib/MC/MCParser/ |
D | MCTargetAsmParser.cpp | 15 const MCSubtargetInfo &STI) in MCTargetAsmParser() argument 17 STI(&STI) in MCTargetAsmParser() 26 STI = &STICopy; in copySTI() 31 return *STI; in getSTI()
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/external/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
D | R600MCCodeEmitter.cpp | 46 const MCSubtargetInfo &STI) const override; 51 const MCSubtargetInfo &STI) const override; 90 const MCSubtargetInfo &STI) const { in encodeInstruction() 99 uint64_t InstWord01 = getBinaryCodeForInstr(MI, Fixups, STI); in encodeInstruction() 101 if (!(STI.getFeatureBits()[AMDGPU::FeatureCaymanISA])) { in encodeInstruction() 123 uint64_t Word01 = getBinaryCodeForInstr(MI, Fixups, STI); in encodeInstruction() 133 uint64_t Inst = getBinaryCodeForInstr(MI, Fixups, STI); in encodeInstruction() 134 if ((STI.getFeatureBits()[AMDGPU::FeatureR600ALUInst]) && in encodeInstruction() 168 const MCSubtargetInfo &STI) const { in getMachineOpValue()
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/external/llvm/lib/Target/BPF/MCTargetDesc/ |
D | BPFMCCodeEmitter.cpp | 45 const MCSubtargetInfo &STI) const; 51 const MCSubtargetInfo &STI) const; 55 const MCSubtargetInfo &STI) const; 59 const MCSubtargetInfo &STI) const override; 78 const MCSubtargetInfo &STI) const { in getMachineOpValue() 109 const MCSubtargetInfo &STI) const { in encodeInstruction() 115 uint64_t Value = getBinaryCodeForInstr(MI, Fixups, STI); in encodeInstruction() 138 uint64_t Value = getBinaryCodeForInstr(MI, Fixups, STI); in encodeInstruction() 155 const MCSubtargetInfo &STI) const { in getMemoryOpValue()
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/external/llvm/lib/Target/X86/ |
D | X86ExpandPseudo.cpp | 44 const X86Subtarget *STI; member in __anon1980611f0111::X86ExpandPseudo 94 bool IsWin64 = STI->isTargetWin64(); in ExpandMI() 137 STI->isTarget64BitLP64() || STI->isTargetNaCl64(); in ExpandMI() 151 TII->get(STI->is64Bit() ? X86::IRET64 : X86::IRET32)); in ExpandMI() 184 STI = &static_cast<const X86Subtarget &>(MF.getSubtarget()); in runOnMachineFunction() 185 TII = STI->getInstrInfo(); in runOnMachineFunction() 186 TRI = STI->getRegisterInfo(); in runOnMachineFunction() 187 X86FL = STI->getFrameLowering(); in runOnMachineFunction()
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