Home
last modified time | relevance | path

Searched refs:SetCC (Results 1 – 25 of 29) sorted by relevance

12

/external/v8/test/cctest/
Dtest-disasm-arm.cc108 COMPARE(and_(r2, r3, Operand(r4), SetCC), in TEST()
115 COMPARE(eor(r4, r5, Operand(r7, LSL, 1), SetCC), in TEST()
119 COMPARE(eor(r4, r5, Operand(r9, LSL, 3), SetCC, cs), in TEST()
124 COMPARE(sub(r5, r6, Operand(r10, LSL, 30), SetCC, cc), in TEST()
128 COMPARE(sub(r5, r6, Operand(r10, LSL, 16), SetCC, mi), in TEST()
135 COMPARE(rsb(r6, r7, Operand(fp, LSR, 0), SetCC), in TEST()
144 COMPARE(add(r7, r8, Operand(ip), SetCC), in TEST()
146 COMPARE(add(r7, r8, Operand(ip, ASR, 31), SetCC, vs), in TEST()
153 COMPARE(adc(r5, sp, Operand(ip), SetCC), in TEST()
155 COMPARE(adc(r8, lr, Operand(ip, ASR, 31), SetCC, vc), in TEST()
[all …]
Dtest-assembler-ppc.cc1000 __ mov(r1, Operand(r1, ASR, 1), SetCC);
1005 __ mov(r2, Operand(r2, ASR, 1), SetCC);
1012 __ mov(r3, Operand(r1, ASR, 1), SetCC); // Set the carry.
1018 __ mov(r3, Operand(r2, ASR, 1), SetCC); // Unset the carry.
Dtest-assembler-arm.cc959 __ mov(r1, Operand(r1, ASR, 1), SetCC);
964 __ mov(r2, Operand(r2, ASR, 1), SetCC);
971 __ mov(r3, Operand(r1, ASR, 1), SetCC); // Set the carry.
977 __ mov(r3, Operand(r2, ASR, 1), SetCC); // Unset the carry.
/external/llvm/test/CodeGen/AArch64/
Dsetcc-takes-i32.ll4 ; correctly. Previously LLVM thought that i64 was the appropriate SetCC output,
8 ; It was expecting the smallest legal promotion of i1 to be the preferred SetCC
/external/v8/src/arm/
Dbuiltins-arm.cc153 __ sub(r0, r0, Operand(1), SetCC); in Generate_NumberConstructor()
188 __ sub(r0, r0, Operand(1), SetCC); in Generate_NumberConstructor_ConstructStub()
253 __ sub(r0, r0, Operand(1), SetCC); in Generate_StringConstructor()
312 __ sub(r0, r0, Operand(1), SetCC); in Generate_StringConstructor_ConstructStub()
623 __ sub(r4, r4, Operand(2), SetCC); in Generate_JSConstructStubHelper()
914 __ sub(r4, r4, Operand(kPointerSize), SetCC); in Generate_InterpreterEntryTrampoline()
1520 __ sub(r4, r0, Operand(1), SetCC); in Generate_FunctionPrototypeApply()
1522 __ sub(r4, r4, Operand(1), SetCC, ge); in Generate_FunctionPrototypeApply()
1630 __ sub(r4, r0, Operand(1), SetCC); in Generate_ReflectApply()
1632 __ sub(r4, r4, Operand(1), SetCC, ge); in Generate_ReflectApply()
[all …]
Dcodegen-arm.cc141 __ sub(chars, chars, Operand(64), SetCC); in CreateMemCopyUint8Function()
200 __ bic(temp1, chars, Operand(0x3), SetCC); in CreateMemCopyUint8Function()
208 __ bic(temp2, chars, Operand(0x3), SetCC); in CreateMemCopyUint8Function()
220 __ mov(chars, Operand(chars, LSL, 31), SetCC); in CreateMemCopyUint8Function()
304 __ mov(chars, Operand(chars, LSL, 31), SetCC); // bit0 => ne, bit1 => cs in CreateMemCopyUint16Uint8Function()
Dmacro-assembler-arm.cc1756 and_(result_end, result, Operand(kDoubleAlignmentMask), SetCC); in Allocate()
1784 add(result_end, source, bits_operand, SetCC, cond); in Allocate()
1859 and_(result_end, result, Operand(kDoubleAlignmentMask), SetCC); in Allocate()
1875 add(result_end, result, Operand(object_size, LSL, kPointerSizeLog2), SetCC); in Allocate()
1877 add(result_end, result, Operand(object_size), SetCC); in Allocate()
2351 sub(result, result, Operand(1), SetCC); in TryInt32Floor()
2698 sub(scratch, reg, Operand(1), SetCC); in JumpIfNotPowerOfTwoOrZero()
2710 sub(scratch, reg, Operand(1), SetCC); in JumpIfNotPowerOfTwoOrZeroAndNeg()
2730 SmiUntag(dst, src, SetCC); in UntagAndJumpIfSmi()
2738 SmiUntag(dst, src, SetCC); in UntagAndJumpIfNotSmi()
[all …]
Dcode-stubs-arm.cc193 __ rsb(scratch, scratch, Operand(51), SetCC); in Generate()
342 __ orr(r0, r3, Operand(r2), SetCC); in EmitIdenticalObjectComparison()
879 __ mov(scratch, Operand(scratch, ASR, 1), SetCC); in Generate()
1792 __ SmiUntag(r9, r2, SetCC); in GenerateNewStrict()
1989 SetCC); in Generate()
2036 __ mov(r3, Operand(r0, ASR, 2), SetCC); in Generate()
2232 __ sub(r1, r1, Operand(1), SetCC); in Generate()
2771 __ add(count, count, Operand(count), SetCC); in GenerateCopyCharacters()
2819 __ mov(r2, Operand(r2, ROR, 1), SetCC); in Generate()
2820 __ mov(r3, Operand(r3, ROR, 1), SetCC, cc); in Generate()
[all …]
Dconstants-arm.h227 SetCC = 1 << 20, // Set condition code. enumerator
/external/llvm/test/Transforms/ConstProp/
D2002-09-03-SetCC-Bools.ll1 ; SetCC on boolean values was not implemented!
/external/llvm/lib/Target/X86/
DX86InstrCMovSetCC.td1 //===-- X86InstrCMovSetCC.td - Conditional Move and SetCC --*- tablegen -*-===//
82 // SetCC instructions.
DX86ISelLowering.cpp14724 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, in LowerSETCC() local
14728 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC); in LowerSETCC()
14729 return SetCC; in LowerSETCC()
14746 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, in LowerSETCC() local
14749 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC); in LowerSETCC()
14750 return SetCC; in LowerSETCC()
16672 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, in LowerINTRINSIC_WO_CHAIN() local
16674 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); in LowerINTRINSIC_WO_CHAIN()
16690 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, in LowerINTRINSIC_WO_CHAIN() local
16692 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); in LowerINTRINSIC_WO_CHAIN()
[all …]
/external/v8/src/compiler/arm/
Dcode-generator-arm.cc58 return SetCC; in OutputSBit()
667 DCHECK_EQ(SetCC, i.OutputSBit()); in AssembleArchInstruction()
671 DCHECK_EQ(SetCC, i.OutputSBit()); in AssembleArchInstruction()
675 DCHECK_EQ(SetCC, i.OutputSBit()); in AssembleArchInstruction()
679 DCHECK_EQ(SetCC, i.OutputSBit()); in AssembleArchInstruction()
691 DCHECK_EQ(SetCC, i.OutputSBit()); in AssembleArchInstruction()
742 DCHECK_EQ(SetCC, i.OutputSBit()); in AssembleArchInstruction()
/external/llvm/lib/Target/Mips/
DMipsISelLowering.cpp586 SDValue SetCC = N->getOperand(0); in performSELECTCombine() local
588 if ((SetCC.getOpcode() != ISD::SETCC) || in performSELECTCombine()
589 !SetCC.getOperand(0).getValueType().isInteger()) in performSELECTCombine()
613 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); in performSELECTCombine()
616 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), in performSELECTCombine()
617 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); in performSELECTCombine()
619 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True); in performSELECTCombine()
642 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False); in performSELECTCombine()
649 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); in performSELECTCombine()
650 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), in performSELECTCombine()
[all …]
DMipsSEISelLowering.cpp1027 SDValue SetCC = N->getOperand(0); in performVSELECTCombine() local
1029 if (SetCC.getOpcode() != MipsISD::SETCC_DSP) in performVSELECTCombine()
1033 SetCC.getOperand(0), SetCC.getOperand(1), in performVSELECTCombine()
1034 N->getOperand(1), N->getOperand(2), SetCC.getOperand(2)); in performVSELECTCombine()
/external/v8/src/regexp/arm/
Dregexp-macro-assembler-arm.cc217 __ sub(r1, r1, r0, SetCC); // Length of capture. in CheckNotBackReferenceIgnoreCase()
353 __ sub(r1, r1, r0, SetCC); // Length to check. in CheckNotBackReference()
650 __ sub(r0, sp, r0, SetCC); in GetCode()
713 __ sub(r2, r2, Operand(1), SetCC); in GetCode()
/external/v8/src/crankshaft/arm/
Dlithium-codegen-arm.cc818 __ sub(r1, r1, Operand(1), SetCC); in DeoptimizeIf()
1027 __ rsb(dividend, dividend, Operand::Zero(), SetCC); in DoModByPowerOf2I()
1054 __ sub(result, dividend, result, SetCC); in DoModByConstI()
1163 __ sub(result_reg, left_reg, scratch, SetCC); in DoModI()
1244 __ sub(scratch0(), scratch0(), dividend, SetCC); in DoDivByConstI()
1356 __ rsb(result, dividend, Operand::Zero(), SetCC); in DoFlooringDivByPowerOf2I()
1512 __ rsb(result, left, Operand::Zero(), SetCC); in DoMulI()
1651 __ mov(result, Operand(left, LSR, scratch), SetCC); in DoShiftI()
1700 __ SmiTag(result, result, SetCC); in DoShiftI()
1702 __ SmiTag(result, left, SetCC); in DoShiftI()
[all …]
/external/v8/src/x87/
Ddisasm-x87.cc336 int SetCC(byte* data);
660 int DisassemblerX87::SetCC(byte* data) { in SetCC() function in disasm::DisassemblerX87
1136 data += SetCC(data); in InstructionDecode()
/external/v8/src/full-codegen/arm/
Dfull-codegen-arm.cc162 __ sub(r2, r2, Operand(1), SetCC); in Generate()
378 __ sub(r3, r3, Operand(Smi::FromInt(delta)), SetCC); in EmitProfilingCounterDecrement()
2118 __ sub(r3, r3, Operand(Smi::FromInt(1)), SetCC); in EmitGeneratorResume()
2172 __ sub(r3, r3, Operand(1), SetCC); in EmitGeneratorResume()
2308 __ add(scratch1, left, Operand(right), SetCC); in EmitInlineSmiBinaryOp()
2313 __ sub(scratch1, left, Operand(right), SetCC); in EmitInlineSmiBinaryOp()
2326 __ add(scratch2, right, Operand(left), SetCC); in EmitInlineSmiBinaryOp()
3776 __ SmiUntag(array_length, SetCC); in EmitFastOneByteArrayJoin()
3813 __ add(string_length, string_length, Operand(scratch), SetCC); in EmitFastOneByteArrayJoin()
3850 __ add(string_length, string_length, Operand(scratch), SetCC); in EmitFastOneByteArrayJoin()
[all …]
/external/v8/src/x64/
Ddisasm-x64.cc477 int SetCC(byte* data);
869 int DisassemblerX64::SetCC(byte* data) { in SetCC() function in disasm::DisassemblerX64
1852 current = data + SetCC(data); in TwoByteOpcodeInstruction()
/external/v8/src/ia32/
Ddisasm-ia32.cc399 int SetCC(byte* data);
724 int DisassemblerIA32::SetCC(byte* data) { in SetCC() function in disasm::DisassemblerIA32
1472 data += SetCC(data); in InstructionDecode()
/external/llvm/test/CodeGen/Generic/
Dselect.ll22 ; A SetCC whose result is used should produce instructions to
/external/llvm/lib/Target/AMDGPU/
DSIISelLowering.cpp1037 SDNode *SetCC = Intr; in LowerBRCOND() local
1038 assert(SetCC->getConstantOperandVal(1) == 1); in LowerBRCOND()
1039 assert(cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() == in LowerBRCOND()
1041 Intr = SetCC->getOperand(0).getNode(); in LowerBRCOND()
/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp8937 SDValue SetCC = N0.getOperand(0); in performAcrossLaneMinMaxReductionCombine() local
8938 EVT SetCCVT = SetCC.getValueType(); in performAcrossLaneMinMaxReductionCombine()
8939 if (SetCC.getOpcode() != ISD::SETCC || !SetCCVT.isVector() || in performAcrossLaneMinMaxReductionCombine()
8943 SDValue VectorOp = SetCC.getOperand(0); in performAcrossLaneMinMaxReductionCombine()
8977 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC->getOperand(2))->get(); in performAcrossLaneMinMaxReductionCombine()
9002 return tryMatchAcrossLaneShuffleForReduction(N, SetCC, Op, DAG); in performAcrossLaneMinMaxReductionCombine()
9519 SDValue SetCC = in performVSelectCombine() local
9523 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC, in performVSelectCombine()
9580 SDValue SetCC = DAG.getNode(ISD::SETCC, DL, CCVT, LHS, RHS, N0.getOperand(2)); in performSelectCombine() local
9584 SDValue Mask = DAG.getVectorShuffle(CCVT, DL, SetCC, SetCC, DUPMask.data()); in performSelectCombine()
/external/llvm/lib/CodeGen/SelectionDAG/
DDAGCombiner.cpp5847 SDNode *SetCC = SetCCs[i]; in ExtendSetCCUses() local
5851 SDValue SOp = SetCC->getOperand(j); in ExtendSetCCUses()
5858 Ops.push_back(SetCC->getOperand(2)); in ExtendSetCCUses()
5859 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0), Ops)); in ExtendSetCCUses()
6166 SDValue SetCC = DAG.getSetCC(DL, SetCCVT, in visitSIGN_EXTEND() local
6168 return DAG.getSelect(DL, VT, SetCC, in visitSIGN_EXTEND()
9381 SDValue SetCC = in visitBRCOND() local
9388 MVT::Other, Chain, SetCC, N2); in visitBRCOND()
9397 DAG.ReplaceAllUsesOfValueWith(N1, SetCC); in visitBRCOND()
9448 SDValue SetCC = DAG.getSetCC(SDLoc(TheXor), in visitBRCOND() local
[all …]

12