| /external/llvm/lib/ExecutionEngine/Interpreter/ |
| D | Execution.cpp | 52 Dest.TY##Val = Src1.TY##Val OP Src2.TY##Val; \
56 GenericValue Src2, Type *Ty) { in executeFAddInst() argument
67 GenericValue Src2, Type *Ty) { in executeFSubInst() argument
78 GenericValue Src2, Type *Ty) { in executeFMulInst() argument
89 GenericValue Src2, Type *Ty) { in executeFDivInst() argument
100 GenericValue Src2, Type *Ty) { in executeFRemInst() argument
103 Dest.FloatVal = fmod(Src1.FloatVal, Src2.FloatVal); in executeFRemInst()
106 Dest.DoubleVal = fmod(Src1.DoubleVal, Src2.DoubleVal); in executeFRemInst()
116 Dest.IntVal = APInt(1,Src1.IntVal.OP(Src2.IntVal)); \
121 assert(Src1.AggregateVal.size() == Src2.AggregateVal.size()); \
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIShrinkInstructions.cpp | 90 const MachineOperand *Src2 = TII->getNamedOperand(MI, AMDGPU::OpName::src2); in canShrink() local
97 if (Src2) { in canShrink()
102 if (!isVGPR(Src2, TRI, MRI) || in canShrink()
271 const MachineOperand *Src2 = in runOnMachineFunction() local
273 if (!Src2->isReg()) in runOnMachineFunction()
275 unsigned SReg = Src2->getReg(); in runOnMachineFunction()
309 const MachineOperand *Src2 = in runOnMachineFunction() local
311 if (Src2) { in runOnMachineFunction()
314 Inst32.addOperand(*Src2); in runOnMachineFunction()
318 assert(Src2->getReg() == AMDGPU::VCC && in runOnMachineFunction()
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| D | SIInstrInfo.cpp | 1064 MachineOperand *Src2 = getNamedOperand(*UseMI, AMDGPU::OpName::src2); in FoldImmediate() local
1073 if (!Src2->isReg() || in FoldImmediate()
1074 (Src2->isReg() && RI.isSGPRClass(MRI->getRegClass(Src2->getReg())))) in FoldImmediate()
1099 unsigned Src2Reg = Src2->getReg(); in FoldImmediate()
1100 unsigned Src2SubReg = Src2->getSubReg(); in FoldImmediate()
1107 Src1->setIsKill(Src2->isKill()); in FoldImmediate()
1114 Src2->ChangeToImmediate(Imm); in FoldImmediate()
1127 if (Src2->isReg() && Src2->getReg() == Reg) { in FoldImmediate()
1155 Src2->ChangeToImmediate(Imm); in FoldImmediate()
1269 const MachineOperand *Src2 = getNamedOperand(*MI, AMDGPU::OpName::src2); in convertToThreeAddress() local
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| D | EvergreenInstructions.td | 280 // Src2 = Width
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| D | SIInstrInfo.td | 1005 class getNumSrcArgs<ValueType Src0, ValueType Src1, ValueType Src2> {
1009 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonGenMux.cpp | 93 const MachineOperand &Src2) const;
172 const MachineOperand &Src2) const { in getMuxOpcode()
173 bool IsReg1 = Src1.isReg(), IsReg2 = Src2.isReg(); in getMuxOpcode()
181 if (Src2.isImm() && isInt<8>(Src2.getImm())) in getMuxOpcode()
262 MachineOperand *Src1 = &Def1->getOperand(2), *Src2 = &Def2->getOperand(2); in genMuxInBlock() local
264 unsigned SR2 = Src2->isReg() ? Src2->getReg() : 0; in genMuxInBlock()
280 MachineOperand *SrcT = (MinX == CI.TrueX) ? Src1 : Src2; in genMuxInBlock()
281 MachineOperand *SrcF = (MinX == CI.FalseX) ? Src1 : Src2; in genMuxInBlock()
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| D | HexagonPeephole.cpp | 160 MachineOperand &Src2 = MI->getOperand(2); in runOnMachineFunction() local
164 unsigned SrcReg = Src2.getReg(); in runOnMachineFunction()
177 MachineOperand &Src2 = MI->getOperand(2); in runOnMachineFunction() local
178 if (Src2.getImm() != 32) in runOnMachineFunction()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZSelectionDAGInfo.cpp | 154 SDValue Src1, SDValue Src2, uint64_t Size) { in emitCLC() argument
166 return DAG.getNode(SystemZISD::CLC_LOOP, DL, VTs, Chain, Src1, Src2, in emitCLC()
169 return DAG.getNode(SystemZISD::CLC, DL, VTs, Chain, Src1, Src2, in emitCLC()
188 SDValue Src1, SDValue Src2, SDValue Size, in EmitTargetCodeForMemcmp() argument
194 Chain = emitCLC(DAG, DL, Chain, Src1, Src2, Bytes); in EmitTargetCodeForMemcmp()
242 SDValue Src1, SDValue Src2, in EmitTargetCodeForStrcmp() argument
246 SDValue Unused = DAG.getNode(SystemZISD::STRCMP, DL, VTs, Chain, Src1, Src2, in EmitTargetCodeForStrcmp()
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| D | SystemZSelectionDAGInfo.h | 41 SDValue Src1, SDValue Src2, SDValue Size,
59 SDValue Src1, SDValue Src2,
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| D | SystemZISelLowering.cpp | 3071 SDValue Src2 = Node->getVal(); in lowerATOMIC_LOAD_OP() local
3078 if (auto *Const = dyn_cast<ConstantSDNode>(Src2)) { in lowerATOMIC_LOAD_OP()
3080 Src2 = DAG.getConstant(-Const->getSExtValue(), DL, Src2.getValueType()); in lowerATOMIC_LOAD_OP()
3104 Src2 = DAG.getNode(ISD::SHL, DL, WideVT, Src2, in lowerATOMIC_LOAD_OP()
3108 Src2 = DAG.getNode(ISD::OR, DL, WideVT, Src2, in lowerATOMIC_LOAD_OP()
3113 SDValue Ops[] = { ChainIn, AlignedAddr, Src2, BitShift, NegBitShift, in lowerATOMIC_LOAD_OP()
3138 SDValue Src2 = Node->getVal(); in lowerATOMIC_LOAD_SUB() local
3140 SDLoc DL(Src2); in lowerATOMIC_LOAD_SUB()
3142 if (auto *Op2 = dyn_cast<ConstantSDNode>(Src2)) { in lowerATOMIC_LOAD_SUB()
3151 Src2); in lowerATOMIC_LOAD_SUB()
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| /external/llvm/lib/Target/X86/ |
| D | X86FixupLEAs.cpp | 370 const MachineOperand &Src2 = MI->getOperand(SrcR1 == DstR ? 3 : 1); in processInstructionForSLM() local
374 .addOperand(Src2); in processInstructionForSLM()
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| D | X86InstrInfo.cpp | 2672 unsigned Src2 = MI->getOperand(2).getReg(); in convertToThreeAddressWithLEA() local
2676 if (Src == Src2) { in convertToThreeAddressWithLEA()
2691 .addReg(Src2, getKillRegState(isKill2)); in convertToThreeAddressWithLEA()
2695 LV->replaceKillInstruction(Src2, MI, InsMI2); in convertToThreeAddressWithLEA()
2888 const MachineOperand &Src2 = MI->getOperand(2); in convertToThreeAddress() local
2892 if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false, in convertToThreeAddress()
2909 if (LV && Src2.isKill()) in convertToThreeAddress()
2919 unsigned Src2 = MI->getOperand(2).getReg(); in convertToThreeAddress() local
2923 Src.getReg(), Src.isKill(), Src2, isKill2); in convertToThreeAddress()
2932 LV->replaceKillInstruction(Src2, MI, NewMI); in convertToThreeAddress()
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| D | X86ISelLowering.cpp | 16346 SDValue Src2 = Op.getOperand(2); in LowerINTRINSIC_WO_CHAIN() local
16349 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2), in LowerINTRINSIC_WO_CHAIN()
16354 SDValue Src2 = Op.getOperand(2); in LowerINTRINSIC_WO_CHAIN() local
16363 return getScalarMaskingNode(DAG.getNode(Opc, dl, VT, Src1, Src2, in LowerINTRINSIC_WO_CHAIN()
16370 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2, in LowerINTRINSIC_WO_CHAIN()
16377 SDValue Src2 = Op.getOperand(2); in LowerINTRINSIC_WO_CHAIN() local
16382 Src2 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src2); in LowerINTRINSIC_WO_CHAIN()
16394 Src1, Src2, Rnd), in LowerINTRINSIC_WO_CHAIN()
16399 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,Src1,Src2), in LowerINTRINSIC_WO_CHAIN()
16404 SDValue Src2 = Op.getOperand(2); in LowerINTRINSIC_WO_CHAIN() local
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcAsmPrinter.cpp | 132 MCOperand &RS1, MCOperand &Src2, MCOperand &RD, in EmitBinary() argument
139 Inst.addOperand(Src2); in EmitBinary()
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| D | SparcISelLowering.cpp | 2823 SDValue Src2 = Op.getOperand(1); in LowerADDC_ADDE_SUBC_SUBE() local
2824 SDValue Src2Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2); in LowerADDC_ADDE_SUBC_SUBE()
2825 SDValue Src2Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src2, in LowerADDC_ADDE_SUBC_SUBE()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGBuilder.cpp | 2708 SDValue Src2 = getValue(I.getOperand(1)); in visitShuffleVector() local
2720 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2, in visitShuffleVector()
2736 VT, Src1, Src2)); in visitShuffleVector()
2744 VT, Src2, Src1)); in visitShuffleVector()
2752 bool Src2U = Src2.getOpcode() == ISD::UNDEF; in visitShuffleVector()
2758 MOps2[0] = Src2; in visitShuffleVector()
2762 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, in visitShuffleVector()
2774 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2, in visitShuffleVector()
2830 SDValue &Src = Input == 0 ? Src1 : Src2; in visitShuffleVector()
2855 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2, in visitShuffleVector()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | R600Instructions.td | 806 // Src2 = Width
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| /external/clang/lib/CodeGen/ |
| D | CGBuiltin.cpp | 6870 llvm::Value *Src2 = CGF.EmitScalarExpr(E->getArg(2)); in emitTernaryFPBuiltin() local
6873 return CGF.Builder.CreateCall(F, {Src0, Src1, Src2}); in emitTernaryFPBuiltin()
6920 llvm::Value *Src2 = EmitScalarExpr(E->getArg(2)); in EmitAMDGPUBuiltinExpr() local
6926 return Builder.CreateCall(F, {Src0, Src1, Src2, Src3ToBool}); in EmitAMDGPUBuiltinExpr()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 9085 unsigned Src2 = MI->getOperand(2).getReg(); in EmitInstrWithCustomInserter() local
9099 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2); in EmitInstrWithCustomInserter()
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