Searched refs:SrcMO (Results 1 – 3 of 3) sorted by relevance
100 MachineOperand &SrcMO = MI->getOperand(1); in processBlock() local103 !IsVSReg(SrcMO.getReg(), MRI)) { in processBlock()108 IsVRReg(SrcMO.getReg(), MRI) ? &PPC::VSHRCRegClass : in processBlock()110 assert((IsF8Reg(SrcMO.getReg(), MRI) || in processBlock()111 IsVRReg(SrcMO.getReg(), MRI) || in processBlock()112 IsVSSReg(SrcMO.getReg(), MRI) || in processBlock()113 IsVSFReg(SrcMO.getReg(), MRI)) && in processBlock()121 .addOperand(SrcMO) in processBlock()122 .addImm(IsVRReg(SrcMO.getReg(), MRI) ? PPC::sub_128 : in processBlock()126 SrcMO.setReg(NewVReg); in processBlock()[all …]
147 MachineOperand &SrcMO = MI->getOperand(1); in LowerCopy() local149 if (SrcMO.getReg() == DstMO.getReg()) { in LowerCopy()153 if (SrcMO.isUndef() || MI->getNumOperands() > 2) { in LowerCopy()167 DstMO.getReg(), SrcMO.getReg(), SrcMO.isKill()); in LowerCopy()
1418 MachineOperand &SrcMO = MI->getOperand(SrcIdx); in collectTiedOperands() local1420 unsigned SrcReg = SrcMO.getReg(); in collectTiedOperands()1426 assert(SrcReg && SrcMO.isUse() && "two address instruction invalid"); in collectTiedOperands()1429 if (SrcMO.isUndef() && !DstMO.getSubReg()) { in collectTiedOperands()1435 SrcMO.setReg(DstReg); in collectTiedOperands()1436 SrcMO.setSubReg(0); in collectTiedOperands()