| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZElimCompare.cpp | 394 unsigned SrcReg2 = (Compare->getOperand(1).isReg() ? in fuseCompareAndBranch() local
399 (SrcReg2 && MBBI->modifiesRegister(SrcReg2, TRI))) in fuseCompareAndBranch()
429 if (SrcReg2) in fuseCompareAndBranch()
430 MBBI->clearRegisterKills(SrcReg2, TRI); in fuseCompareAndBranch()
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| D | SystemZInstrInfo.h | 155 unsigned &SrcReg2, int &Mask, int &Value) const override;
157 unsigned SrcReg2, int Mask, int Value,
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| D | SystemZInstrInfo.cpp | 406 unsigned &SrcReg, unsigned &SrcReg2, in analyzeCompare() argument
414 SrcReg2 = 0; in analyzeCompare()
490 unsigned SrcReg, unsigned SrcReg2, in optimizeCompareInstr() argument
493 assert(!SrcReg2 && "Only optimizing constant comparisons so far"); in optimizeCompareInstr()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.h | 252 unsigned &SrcReg, unsigned &SrcReg2,
256 unsigned SrcReg, unsigned SrcReg2,
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| D | PPCFastISel.cpp | 863 unsigned SrcReg2 = 0; in PPCEmitCmp() local
865 SrcReg2 = getRegForValue(SrcValue2); in PPCEmitCmp()
866 if (SrcReg2 == 0) in PPCEmitCmp()
878 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
880 SrcReg2 = ExtReg; in PPCEmitCmp()
886 .addReg(SrcReg1).addReg(SrcReg2); in PPCEmitCmp()
1250 unsigned SrcReg2 = getRegForValue(I->getOperand(1)); in SelectBinaryIntOp() local
1251 if (SrcReg2 == 0) return false; in SelectBinaryIntOp()
1255 std::swap(SrcReg1, SrcReg2); in SelectBinaryIntOp()
1258 .addReg(SrcReg1).addReg(SrcReg2); in SelectBinaryIntOp()
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| D | PPCInstrInfo.cpp | 1477 unsigned &SrcReg, unsigned &SrcReg2, in analyzeCompare() argument
1488 SrcReg2 = 0; in analyzeCompare()
1499 SrcReg2 = MI->getOperand(2).getReg(); in analyzeCompare()
1505 unsigned SrcReg, unsigned SrcReg2, in optimizeCompareInstr() argument
1606 if (SrcReg2 != 0) in optimizeCompareInstr()
1645 Instr.getOperand(2).getReg() == SrcReg2) || in optimizeCompareInstr()
1646 (Instr.getOperand(1).getReg() == SrcReg2 && in optimizeCompareInstr()
1692 ShouldSwap = SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 && in optimizeCompareInstr()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.h | 158 unsigned &SrcReg2, int &CmpMask,
163 unsigned SrcReg2, int CmpMask, int CmpValue,
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| D | AArch64InstrInfo.cpp | 652 unsigned &SrcReg2, int &CmpMask, in analyzeCompare() argument
671 SrcReg2 = MI->getOperand(2).getReg(); in analyzeCompare()
680 SrcReg2 = 0; in analyzeCompare()
690 SrcReg2 = 0; in analyzeCompare()
828 MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, in optimizeCompareInstr() argument
856 if (CmpValue != 0 || SrcReg2 != 0) in optimizeCompareInstr()
2628 unsigned SrcReg2 = Root.getOperand(IdxOtherOpd).getReg(); in genMadd() local
2637 if (TargetRegisterInfo::isVirtualRegister(SrcReg2)) in genMadd()
2638 MRI.constrainRegClass(SrcReg2, RC); in genMadd()
2644 .addReg(SrcReg2, getKillRegState(Src2IsKill)); in genMadd()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 1434 unsigned SrcReg2 = 0; in ARMEmitCmp() local
1436 SrcReg2 = getRegForValue(Src2Value); in ARMEmitCmp()
1437 if (SrcReg2 == 0) return false; in ARMEmitCmp()
1445 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt); in ARMEmitCmp()
1446 if (SrcReg2 == 0) return false; in ARMEmitCmp()
1453 SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1); in ARMEmitCmp()
1455 .addReg(SrcReg1).addReg(SrcReg2)); in ARMEmitCmp()
1772 unsigned SrcReg2 = getRegForValue(I->getOperand(1)); in SelectBinaryIntOp() local
1773 if (SrcReg2 == 0) return false; in SelectBinaryIntOp()
1777 SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2); in SelectBinaryIntOp()
[all …]
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| D | ARMBaseInstrInfo.h | 256 unsigned &SrcReg2, int &CmpMask,
264 unsigned SrcReg2, int CmpMask, int CmpValue,
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| D | ARMBaseInstrInfo.cpp | 2285 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, in analyzeCompare() argument
2292 SrcReg2 = 0; in analyzeCompare()
2299 SrcReg2 = MI->getOperand(1).getReg(); in analyzeCompare()
2306 SrcReg2 = 0; in analyzeCompare()
2359 unsigned SrcReg2, int ImmValue, in isRedundantFlagInstr() argument
2366 OI->getOperand(2).getReg() == SrcReg2) || in isRedundantFlagInstr()
2367 (OI->getOperand(1).getReg() == SrcReg2 && in isRedundantFlagInstr()
2389 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, in optimizeCompareInstr() argument
2427 if (SrcReg2 != 0) in optimizeCompareInstr()
2456 if (isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) { in optimizeCompareInstr()
[all …]
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrInfo.h | 506 unsigned &SrcReg2, int &CmpMask,
513 unsigned SrcReg2, int CmpMask, int CmpValue,
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| D | X86InstrInfo.cpp | 2890 unsigned SrcReg2; in convertToThreeAddress() local
2893 SrcReg2, isKill2, isUndef2, ImplicitOp2)) in convertToThreeAddress()
2903 NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2); in convertToThreeAddress()
2910 LV->replaceKillInstruction(SrcReg2, MI, NewMI); in convertToThreeAddress()
4697 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, in analyzeCompare() argument
4709 SrcReg2 = 0; in analyzeCompare()
4719 SrcReg2 = 0; in analyzeCompare()
4728 SrcReg2 = MI->getOperand(2).getReg(); in analyzeCompare()
4740 SrcReg2 = 0; in analyzeCompare()
4749 SrcReg2 = MI->getOperand(1).getReg(); in analyzeCompare()
[all …]
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| /external/llvm/lib/CodeGen/ |
| D | PeepholeOptimizer.cpp | 566 unsigned SrcReg, SrcReg2; in optimizeCmpInstr() local
568 if (!TII->analyzeCompare(MI, SrcReg, SrcReg2, CmpMask, CmpValue) || in optimizeCmpInstr()
570 (SrcReg2 != 0 && TargetRegisterInfo::isPhysicalRegister(SrcReg2))) in optimizeCmpInstr()
574 if (TII->optimizeCompareInstr(MI, SrcReg, SrcReg2, CmpMask, CmpValue, MRI)) { in optimizeCmpInstr()
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| /external/llvm/include/llvm/Target/ |
| D | TargetInstrInfo.h | 1096 unsigned &SrcReg, unsigned &SrcReg2, in analyzeCompare() argument
1105 unsigned SrcReg, unsigned SrcReg2, in optimizeCompareInstr() argument
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.h | 231 unsigned &SrcReg, unsigned &SrcReg2,
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| D | HexagonInstrInfo.cpp | 1290 unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const { in analyzeCompare() argument
1350 SrcReg2 = MI->getOperand(2).getReg(); in analyzeCompare()
1365 SrcReg2 = 0; in analyzeCompare()
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| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| D | radeon_program_alu.c | 83 struct rc_src_register SrcReg2) in emit3() argument
95 fpi->U.I.SrcReg[2] = SrcReg2; in emit3()
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