| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDGPURegisterInfo.td | 15 def sel_x : SubRegIndex;
16 def sel_y : SubRegIndex;
17 def sel_z : SubRegIndex;
18 def sel_w : SubRegIndex;
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| D | R600ExpandSpecialInstrs.cpp | 105 unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan); in runOnMachineFunction() local
106 Src0 = TRI.getSubReg(Src0, SubRegIndex); in runOnMachineFunction()
107 Src1 = TRI.getSubReg(Src1, SubRegIndex); in runOnMachineFunction()
119 unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan); in runOnMachineFunction() local
120 DstReg = TRI.getSubReg(DstReg, SubRegIndex); in runOnMachineFunction()
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| D | R600InstrInfo.cpp | 57 unsigned SubRegIndex = RI.getSubRegFromChannel(I); in copyPhysReg() local
59 .addReg(RI.getSubReg(DestReg, SubRegIndex), RegState::Define) in copyPhysReg()
60 .addReg(RI.getSubReg(SrcReg, SubRegIndex)) in copyPhysReg()
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| D | AMDGPUInstructions.td | 134 SubRegIndex sub_reg>: Pat<
142 int sub_idx, SubRegIndex sub_reg> : Pat <
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterInfo.td | 23 def sub_32 : SubRegIndex<32>;
25 def bsub : SubRegIndex<8>;
26 def hsub : SubRegIndex<16>;
27 def ssub : SubRegIndex<32>;
28 def dsub : SubRegIndex<32>;
29 def sube32 : SubRegIndex<32>;
30 def subo32 : SubRegIndex<32>;
31 def qhisub : SubRegIndex<64>;
32 def qsub : SubRegIndex<64>;
33 def sube64 : SubRegIndex<64>;
[all …]
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| D | AArch64InstrInfo.td | 1308 SubRegIndex sub> {
2019 SubRegIndex SubRegIdx,
3340 SubRegIndex sub> {
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| /external/llvm/lib/Target/AMDGPU/ |
| D | R600ExpandSpecialInstrs.cpp | 286 unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan); in runOnMachineFunction() local
287 Src0 = TRI.getSubReg(Src0, SubRegIndex); in runOnMachineFunction()
288 Src1 = TRI.getSubReg(Src1, SubRegIndex); in runOnMachineFunction()
301 unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan); in runOnMachineFunction() local
302 DstReg = TRI.getSubReg(DstReg, SubRegIndex); in runOnMachineFunction()
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| D | AMDGPURegisterInfo.td | 17 def sub#Index : SubRegIndex<32, !shl(Index, 5)>;
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| D | SIInstructions.td | 2493 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index)
2496 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index)
2500 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index)
2503 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index)
2509 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index)
2512 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index)
2516 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index)
2519 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index)
2525 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index)
2528 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index)
[all …]
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| D | R600InstrInfo.cpp | 66 unsigned SubRegIndex = RI.getSubRegFromChannel(I); in copyPhysReg() local
68 RI.getSubReg(DestReg, SubRegIndex), in copyPhysReg()
69 RI.getSubReg(SrcReg, SubRegIndex)) in copyPhysReg()
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| D | AMDGPUInstructions.td | 515 SubRegIndex sub_reg>
523 int sub_idx, SubRegIndex sub_reg>
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZRegisterInfo.td | 24 def subreg_l32 : SubRegIndex<32, 0>; // Also acts as subreg_ll32.
25 def subreg_h32 : SubRegIndex<32, 32>; // Also acts as subreg_lh32.
26 def subreg_l64 : SubRegIndex<64, 0>;
27 def subreg_h64 : SubRegIndex<64, 64>;
28 def subreg_r32 : SubRegIndex<32, 32>; // Reinterpret a wider reg as 32 bits.
29 def subreg_r64 : SubRegIndex<64, 64>; // Reinterpret a wider reg as 64 bits.
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| D | SystemZInstrVector.td | 996 SubRegIndex subreg> {
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| /external/llvm/lib/Target/ARM/ |
| D | ARMRegisterInfo.td | 30 def qqsub_0 : SubRegIndex<256>;
31 def qqsub_1 : SubRegIndex<256, 256>;
34 def qsub_0 : SubRegIndex<128>;
35 def qsub_1 : SubRegIndex<128, 128>;
39 def dsub_0 : SubRegIndex<64>;
40 def dsub_1 : SubRegIndex<64, 64>;
48 def ssub_0 : SubRegIndex<32>;
49 def ssub_1 : SubRegIndex<32, 32>;
53 def gsub_0 : SubRegIndex<32>;
54 def gsub_1 : SubRegIndex<32, 32>;
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| /external/llvm/lib/Target/Mips/ |
| D | MipsRegisterInfo.td | 14 def sub_32 : SubRegIndex<32>;
15 def sub_64 : SubRegIndex<64>;
16 def sub_lo : SubRegIndex<32>;
17 def sub_hi : SubRegIndex<32, 32>;
18 def sub_dsp16_19 : SubRegIndex<4, 16>;
19 def sub_dsp20 : SubRegIndex<1, 20>;
20 def sub_dsp21 : SubRegIndex<1, 21>;
21 def sub_dsp22 : SubRegIndex<1, 22>;
22 def sub_dsp23 : SubRegIndex<1, 23>;
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.td | 14 def sub_lt : SubRegIndex<1>;
15 def sub_gt : SubRegIndex<1, 1>;
16 def sub_eq : SubRegIndex<1, 2>;
17 def sub_un : SubRegIndex<1, 3>;
18 def sub_32 : SubRegIndex<32>;
19 def sub_64 : SubRegIndex<64>;
20 def sub_128 : SubRegIndex<128>;
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| /external/llvm/include/llvm/Target/ |
| D | Target.td | 24 // SubRegIndex - Use instances of SubRegIndex to identify subregisters.
25 class SubRegIndex<int size, int offset = 0> {
37 // ComposedOf - A list of two SubRegIndex instances, [A, B].
38 // This indicates that this SubRegIndex is the result of composing A and B.
40 list<SubRegIndex> ComposedOf = [];
56 // the synthetic index dsub_1_dsub_2 unless some SubRegIndex is defined with
58 list<SubRegIndex> CoveringSubRegIndices = [];
63 class ComposedSubRegIndex<SubRegIndex A, SubRegIndex B>
64 : SubRegIndex<B.Size, !if(!eq(A.Offset, -1), -1,
67 // See SubRegIndex.
[all …]
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| D | TargetRegisterInfo.h | 552 static void dumpReg(unsigned Reg, unsigned SubRegIndex = 0,
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcRegisterInfo.td | 25 def sub_even : SubRegIndex<32>;
26 def sub_odd : SubRegIndex<32, 32>;
27 def sub_even64 : SubRegIndex<64>;
28 def sub_odd64 : SubRegIndex<64, 64>;
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| /external/llvm/lib/CodeGen/ |
| D | TargetRegisterInfo.cpp | 393 TargetRegisterInfo::dumpReg(unsigned Reg, unsigned SubRegIndex, in dumpReg() argument
395 dbgs() << PrintReg(Reg, TRI, SubRegIndex) << "\n"; in dumpReg()
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| /external/llvm/lib/Target/X86/ |
| D | X86RegisterInfo.td | 24 def sub_8bit : SubRegIndex<8>;
25 def sub_8bit_hi : SubRegIndex<8, 8>;
26 def sub_16bit : SubRegIndex<16>;
27 def sub_32bit : SubRegIndex<32>;
28 def sub_xmm : SubRegIndex<128>;
29 def sub_ymm : SubRegIndex<256>;
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.td | 82 def subreg_loreg : SubRegIndex<32>;
83 def subreg_hireg : SubRegIndex<32, 32>;
84 def subreg_overflow : SubRegIndex<1, 0>;
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| /external/llvm/lib/Target/AVR/ |
| D | AVRRegisterInfo.td | 32 def sub_lo : SubRegIndex<8>;
33 def sub_hi : SubRegIndex<8, 8>;
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430RegisterInfo.td | 46 def subreg_8bit : SubRegIndex<8> { let Namespace = "MSP430"; }
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| /external/llvm/utils/TableGen/ |
| D | CodeGenRegisters.cpp | 1265 for (const auto &SubRegIndex : SubRegIndices) { in computeSubRegLaneMasks() local
1266 if (RegClass.getSubClassWithSubReg(&SubRegIndex) == nullptr) in computeSubRegLaneMasks()
1268 LaneMask |= SubRegIndex.LaneMask; in computeSubRegLaneMasks()
1784 CodeGenSubRegIndex *SubRegIndex = S->first; in computeRegUnitLaneMasks() local
1786 unsigned LaneMask = SubRegIndex->LaneMask; in computeRegUnitLaneMasks()
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