| /external/llvm/lib/CodeGen/ |
| D | AggressiveAntiDepBreaker.cpp | 556 unsigned SuperReg = 0; in FindSuitableFreeRegisters() local
559 if ((SuperReg == 0) || TRI->isSuperRegister(SuperReg, Reg)) in FindSuitableFreeRegisters()
560 SuperReg = Reg; in FindSuitableFreeRegisters()
579 if (Reg == SuperReg) continue; in FindSuitableFreeRegisters()
580 bool IsSub = TRI->isSubRegister(SuperReg, Reg); in FindSuitableFreeRegisters()
595 dbgs() << "*** Performing rename " << TRI->getName(SuperReg) << in FindSuitableFreeRegisters()
609 TRI->getMinimalPhysRegClass(SuperReg, MVT::Other); in FindSuitableFreeRegisters()
631 if (NewSuperReg == SuperReg) continue; in FindSuitableFreeRegisters()
642 if (Reg == SuperReg) { in FindSuitableFreeRegisters()
645 unsigned NewSubRegIdx = TRI->getSubRegIndex(SuperReg, Reg); in FindSuitableFreeRegisters()
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| D | ScheduleDAGInstrs.cpp | 1235 const unsigned SuperReg = MO.getReg(); in toggleKillFlag() local
1237 for (MCSubRegIterator SubRegs(SuperReg, TRI); SubRegs.isValid(); ++SubRegs) { in toggleKillFlag()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 823 unsigned SuperReg = in copyPhysReg() local
826 if (VSXSelfCopyCrash && SrcReg == SuperReg) in copyPhysReg()
829 DestReg = SuperReg; in copyPhysReg()
832 unsigned SuperReg = in copyPhysReg() local
835 if (VSXSelfCopyCrash && SrcReg == SuperReg) in copyPhysReg()
838 DestReg = SuperReg; in copyPhysReg()
841 unsigned SuperReg = in copyPhysReg() local
844 if (VSXSelfCopyCrash && DestReg == SuperReg) in copyPhysReg()
847 SrcReg = SuperReg; in copyPhysReg()
850 unsigned SuperReg = in copyPhysReg() local
[all …]
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.h | 31 MachineOperand &SuperReg,
37 MachineOperand &SuperReg,
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| D | SIInstrInfo.cpp | 1708 MachineOperand &SuperReg, in buildExtractSubReg() argument
1717 if (SuperReg.getSubReg() == AMDGPU::NoSubRegister) { in buildExtractSubReg()
1719 .addReg(SuperReg.getReg(), 0, SubIdx); in buildExtractSubReg()
1730 .addReg(SuperReg.getReg(), 0, SuperReg.getSubReg()); in buildExtractSubReg()
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| D | R600InstrInfo.cpp | 1085 unsigned SuperReg = AMDGPU::R600_Reg128RegClass.getRegister(Index); in reserveIndirectRegisters() local
1086 Reserved.set(SuperReg); in reserveIndirectRegisters()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 1924 SDValue SuperReg = SDValue(VLd, 0); in SelectVLD() local
1930 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg)); in SelectVLD()
2158 SDValue SuperReg; in SelectVLDSTLane() local
2163 SuperReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0); in SelectVLDSTLane()
2165 SuperReg = SDValue(createQRegPairNode(MVT::v4i64, V0, V1), 0); in SelectVLDSTLane()
2172 SuperReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0); in SelectVLDSTLane()
2174 SuperReg = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0); in SelectVLDSTLane()
2176 Ops.push_back(SuperReg); in SelectVLDSTLane()
2190 SuperReg = SDValue(VLdLn, 0); in SelectVLDSTLane()
2196 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg)); in SelectVLDSTLane()
[all …]
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 1146 SDValue SuperReg = SDValue(Ld, 0); in SelectLoad() local
1149 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg)); in SelectLoad()
1174 SDValue SuperReg = SDValue(Ld, 1); in SelectPostLoad() local
1176 ReplaceUses(SDValue(N, 0), SuperReg); in SelectPostLoad()
1180 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg)); in SelectPostLoad()
1282 SDValue SuperReg = SDValue(Ld, 0); in SelectLoadLane() local
1288 SDValue NV = CurDAG->getTargetExtractSubreg(QSubs[i], dl, WideVT, SuperReg); in SelectLoadLane()
1332 SDValue SuperReg = SDValue(Ld, 1); in SelectPostLoadLane() local
1335 Narrow ? NarrowVector(SuperReg, *CurDAG) : SuperReg); in SelectPostLoadLane()
1342 SuperReg); in SelectPostLoadLane()
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 5927 unsigned SuperReg = MRI->getMatchingSuperReg( in ParseInstruction() local
5930 assert(SuperReg && "expected register pair"); in ParseInstruction()
5932 unsigned PairedReg = MRI->getSubReg(SuperReg, ARM::gsub_1); in ParseInstruction()
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