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Searched refs:TGSI_OPCODE_DDX (Results 1 – 16 of 16) sorted by relevance

/external/mesa3d/src/gallium/auxiliary/tgsi/
Dtgsi_util.c206 case TGSI_OPCODE_DDX: in tgsi_util_get_inst_usage_mask()
Dtgsi_info.c77 { 1, 1, 0, 0, 0, 0, COMP, "DDX", TGSI_OPCODE_DDX },
Dtgsi_exec.c3588 case TGSI_OPCODE_DDX: in exec_instruction()
/external/mesa3d/src/gallium/include/pipe/
Dp_shader_tokens.h294 #define TGSI_OPCODE_DDX 37 macro
/external/mesa3d/src/gallium/drivers/r600/
Dr600_llvm.c235 bld_base->op_actions[TGSI_OPCODE_DDX].emit = llvm_emit_tex; in r600_tgsi_llvm()
Dr600_shader.c5280 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
5454 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
5628 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
/external/mesa3d/src/gallium/drivers/r300/
Dr300_tgsi_to_rc.c70 case TGSI_OPCODE_DDX: return RC_OPCODE_DDX; in translate_opcode()
/external/mesa3d/src/gallium/drivers/radeon/
Dradeon_setup_tgsi_llvm.c1076 bld_base->op_actions[TGSI_OPCODE_DDX].intr_name = "llvm.AMDGPU.ddx"; in radeon_llvm_context_init()
1077 bld_base->op_actions[TGSI_OPCODE_DDX].fetch_args = tex_fetch_args; in radeon_llvm_context_init()
/external/mesa3d/src/gallium/drivers/svga/
Dsvga_tgsi_insn.c1862 case TGSI_OPCODE_DDX: in emit_deriv()
2542 case TGSI_OPCODE_DDX: in svga_emit_instruction()
3143 emit->info.opcode_count[TGSI_OPCODE_DDX] >= 1 || in needs_to_create_zero()
/external/mesa3d/src/mesa/state_tracker/
Dst_mesa_to_tgsi.c553 return TGSI_OPCODE_DDX; in translate_opcode()
Dst_glsl_to_tgsi.cpp1457 emit(ir, TGSI_OPCODE_DDX, result_dst, op[0]); in visit()
/external/mesa3d/src/gallium/auxiliary/gallivm/
Dlp_bld_tgsi_aos.c662 case TGSI_OPCODE_DDX: in lp_emit_instruction_aos()
Dlp_bld_tgsi_soa.c2111 bld.bld_base.op_actions[TGSI_OPCODE_DDX].emit = ddx_emit; in lp_build_tgsi_soa()
/external/mesa3d/src/gallium/drivers/i915/
Di915_fpc_translate.c584 case TGSI_OPCODE_DDX: in i915_translate_instruction()
/external/mesa3d/src/gallium/drivers/nv30/
Dnvfx_fragprog.c558 case TGSI_OPCODE_DDX: in nvfx_fragprog_parse_instruction()
/external/mesa3d/src/gallium/drivers/nv50/codegen/
Dnv50_ir_from_tgsi.cpp1800 case TGSI_OPCODE_DDX: in handleInstruction()