Searched refs:TGSI_OPCODE_SHL (Results 1 – 10 of 10) sorted by relevance
| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| D | tgsi_info.c | 127 { 1, 2, 0, 0, 0, 0, COMP, "SHL", TGSI_OPCODE_SHL },
291 case TGSI_OPCODE_SHL: in tgsi_opcode_infer_src_type()
339 case TGSI_OPCODE_SHL: in tgsi_opcode_infer_dst_type()
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| D | tgsi_exec.c | 3906 case TGSI_OPCODE_SHL: in exec_instruction()
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| /external/mesa3d/src/gallium/include/pipe/ |
| D | p_shader_tokens.h | 342 #define TGSI_OPCODE_SHL 87 macro
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| /external/mesa3d/src/gallium/auxiliary/gallivm/ |
| D | lp_bld_tgsi_aos.c | 902 case TGSI_OPCODE_SHL: in lp_emit_instruction_aos()
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| D | lp_bld_tgsi_action.c | 1604 bld_base->op_actions[TGSI_OPCODE_SHL].emit = shl_emit_cpu; in lp_set_default_actions_cpu()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | radeon_setup_tgsi_llvm.c | 1067 bld_base->op_actions[TGSI_OPCODE_SHL].emit = emit_shl; in radeon_llvm_context_init()
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| /external/mesa3d/src/gallium/drivers/r600/ |
| D | r600_shader.c | 5332 {TGSI_OPCODE_SHL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT, tgsi_op2_trans},
5506 {TGSI_OPCODE_SHL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT, tgsi_op2},
5680 {TGSI_OPCODE_SHL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT, tgsi_op2},
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| /external/mesa3d/src/gallium/drivers/svga/ |
| D | svga_tgsi_insn.c | 2659 case TGSI_OPCODE_SHL: in svga_emit_instruction()
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| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| D | nv50_ir_from_tgsi.cpp | 1770 case TGSI_OPCODE_SHL: in handleInstruction()
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| /external/mesa3d/src/mesa/state_tracker/ |
| D | st_glsl_to_tgsi.cpp | 1852 emit(ir, TGSI_OPCODE_SHL, result_dst, op[0], op[1]); in visit()
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