Searched refs:TSR (Results 1 – 2 of 2) sorted by relevance
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrHTM.td | 63 def TSR : XForm_htm2 <31, 750,
131 (TSR (HTM_get_imm imm:$L))>;
164 (TSR 1)>;
167 (TSR 0)>;
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonEarlyIfConv.cpp | 783 unsigned TR = 0, TSR = 0, FR = 0, FSR = 0, SR = 0, SSR = 0; in updatePhiNodes() local
789 TR = RO.getReg(), TSR = RO.getSubReg(); in updatePhiNodes()
798 TR = SR, TSR = SSR; in updatePhiNodes()
816 .addReg(TR, 0, TSR) in updatePhiNodes()
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