Searched refs:Tmp6 (Results 1 – 5 of 5) sorted by relevance
| /external/llvm/lib/CodeGen/ |
| D | IntrinsicLowering.cpp | 208 Value *Tmp6 = Builder.CreateShl(V, ConstantInt::get(V->getType(), 24), in LowerBSWAP() local
227 Tmp6 = Builder.CreateAnd(Tmp6, in LowerBSWAP()
248 Tmp6 = Builder.CreateOr(Tmp6, Tmp5, "bswap.or2"); in LowerBSWAP()
251 Tmp8 = Builder.CreateOr(Tmp8, Tmp6, "bswap.or5"); in LowerBSWAP()
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| /external/clang/lib/CodeGen/ |
| D | CGExprComplex.cpp | 785 llvm::Value *Tmp6 = Builder.CreateAdd(Tmp4, Tmp5); // cc+dd in EmitBinDiv() local
792 DSTr = Builder.CreateUDiv(Tmp3, Tmp6); in EmitBinDiv()
793 DSTi = Builder.CreateUDiv(Tmp9, Tmp6); in EmitBinDiv()
795 DSTr = Builder.CreateSDiv(Tmp3, Tmp6); in EmitBinDiv()
796 DSTi = Builder.CreateSDiv(Tmp9, Tmp6); in EmitBinDiv()
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| /external/llvm/lib/Transforms/Utils/ |
| D | IntegerDivision.cpp | 311 Value *Tmp6 = Builder.CreateLShr(Q_2, MSB); in generateUnsignedDivisionCode() local
312 Value *Tmp7 = Builder.CreateOr(Tmp5, Tmp6); in generateUnsignedDivisionCode()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeDAG.cpp | 2840 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; in ExpandBSWAP() local
2861 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT)); in ExpandBSWAP()
2869 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, in ExpandBSWAP()
2880 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5); in ExpandBSWAP()
2883 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6); in ExpandBSWAP()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 6661 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5); in LowerSHL_PARTS() local
6662 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6); in LowerSHL_PARTS()
6690 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5); in LowerSRL_PARTS() local
6691 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6); in LowerSRL_PARTS()
6718 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5); in LowerSRA_PARTS() local
6721 Tmp4, Tmp6, ISD::SETLE); in LowerSRA_PARTS()
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