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Searched refs:TmpReg (Results 1 – 19 of 19) sorted by relevance

/external/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp946 unsigned TmpReg = createResultReg(&PPC::G8RCRegClass); in PPCMoveToFPReg() local
947 if (!PPCEmitIntExt(MVT::i32, SrcReg, MVT::i64, TmpReg, !IsSigned)) in PPCMoveToFPReg()
949 SrcReg = TmpReg; in PPCMoveToFPReg()
1025 unsigned TmpReg = createResultReg(&PPC::G8RCRegClass); in SelectIToFP() local
1026 if (!PPCEmitIntExt(SrcVT, SrcReg, MVT::i64, TmpReg, !IsSigned)) in SelectIToFP()
1029 SrcReg = TmpReg; in SelectIToFP()
1125 unsigned TmpReg = createResultReg(&PPC::F8RCRegClass); in SelectFPToI() local
1127 TII.get(TargetOpcode::COPY_TO_REGCLASS), TmpReg) in SelectFPToI()
1129 SrcReg = TmpReg; in SelectFPToI()
1336 unsigned TmpReg = createResultReg(RC); in processCallArgs() local
[all …]
DPPCFrameLowering.cpp1661 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0; in eliminateCallFramePseudoInstr() local
1675 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) in eliminateCallFramePseudoInstr()
1677 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) in eliminateCallFramePseudoInstr()
1678 .addReg(TmpReg, RegState::Kill) in eliminateCallFramePseudoInstr()
1682 .addReg(TmpReg); in eliminateCallFramePseudoInstr()
DPPCISelLowering.cpp8172 unsigned TmpReg = (!BinOpcode) ? incr : in EmitAtomicBinary() local
8191 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest); in EmitAtomicBinary()
8193 .addReg(TmpReg).addReg(ptrA).addReg(ptrB); in EmitAtomicBinary()
8256 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC); in EmitPartwordAtomicBinary() local
8314 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg) in EmitPartwordAtomicBinary()
8319 .addReg(TmpReg).addReg(MaskReg); in EmitPartwordAtomicBinary()
8975 unsigned TmpReg = RegInfo.createVirtualRegister(RC); in EmitInstrWithCustomInserter() local
9047 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg) in EmitInstrWithCustomInserter()
9050 .addReg(TmpReg).addReg(OldVal3Reg); in EmitInstrWithCustomInserter()
9077 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg) in EmitInstrWithCustomInserter()
/external/llvm/lib/Target/Mips/AsmParser/
DMipsAsmParser.cpp2182 unsigned TmpReg = DstReg; in loadImmediate() local
2189 TmpReg = ATReg; in loadImmediate()
2209 unsigned TmpReg = DstReg; in loadImmediate() local
2211 TmpReg = getATReg(IDLoc); in loadImmediate()
2212 if (!TmpReg) in loadImmediate()
2216 emitRRI(Mips::ORi, TmpReg, ZeroReg, ImmValue, IDLoc, Instructions); in loadImmediate()
2218 emitRRR(ABI.GetPtrAdduOp(), DstReg, TmpReg, SrcReg, IDLoc, Instructions); in loadImmediate()
2232 emitRI(Mips::LUi, TmpReg, 0xffff, IDLoc, Instructions); in loadImmediate()
2233 emitRRI(Mips::DSRL32, TmpReg, TmpReg, 0, IDLoc, Instructions); in loadImmediate()
2235 emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, Instructions); in loadImmediate()
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/external/llvm/lib/Target/ARM/
DMLxExpansionPass.cpp290 unsigned TmpReg = MRI->createVirtualRegister( in ExpandFPMLxInstruction() local
293 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID1, TmpReg) in ExpandFPMLxInstruction()
305 MIB.addReg(TmpReg, getKillRegState(true)) in ExpandFPMLxInstruction()
308 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true)); in ExpandFPMLxInstruction()
DThumbRegisterInfo.cpp572 unsigned TmpReg = MI.getOperand(0).getReg(); in eliminateFrameIndex() local
576 emitThumbRegPlusImmInReg(MBB, II, dl, TmpReg, FrameReg, in eliminateFrameIndex()
579 emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset); in eliminateFrameIndex()
583 emitThumbRegPlusImmediate(MBB, II, dl, TmpReg, FrameReg, Offset, TII, in eliminateFrameIndex()
588 MI.getOperand(FIOperandNum).ChangeToRegister(TmpReg, false, false, true); in eliminateFrameIndex()
DARMISelLowering.cpp8162 unsigned TmpReg = MRI.createVirtualRegister(isThumb1 ? &ARM::tGPRRegClass in attachMEMCPYScratchRegs() local
8164 MIB.addReg(TmpReg, RegState::Define|RegState::Dead); in attachMEMCPYScratchRegs()
/external/llvm/lib/Target/AMDGPU/
DSIFixSGPRCopies.cpp227 unsigned TmpReg = MRI.createVirtualRegister(NewSrcRC); in foldVGPRCopyIntoRegSequence() local
229 BuildMI(*MI.getParent(), &MI, MI.getDebugLoc(), TII->get(AMDGPU::COPY), TmpReg) in foldVGPRCopyIntoRegSequence()
232 MI.getOperand(I).setReg(TmpReg); in foldVGPRCopyIntoRegSequence()
DSIRegisterInfo.cpp384 unsigned TmpReg = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, SPAdj); in eliminateFrameIndex() local
386 TII->get(AMDGPU::V_MOV_B32_e32), TmpReg) in eliminateFrameIndex()
388 FIOp.ChangeToRegister(TmpReg, false, false, true); in eliminateFrameIndex()
DSIInstrInfo.cpp680 RegScavenger *RS, unsigned TmpReg, in calculateLDSSpillAddress() argument
769 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADD_I32_e32), TmpReg) in calculateLDSSpillAddress()
773 return TmpReg; in calculateLDSSpillAddress()
2632 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in lowerScalarAbs() local
2635 BuildMI(MBB, MII, DL, get(AMDGPU::V_SUB_I32_e32), TmpReg) in lowerScalarAbs()
2641 .addReg(TmpReg); in lowerScalarAbs()
2856 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in splitScalar64BitBFE() local
2859 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e64), TmpReg) in splitScalar64BitBFE()
2866 .addReg(TmpReg) in splitScalar64BitBFE()
DSIInstrInfo.h106 unsigned TmpReg,
/external/llvm/lib/Target/X86/AsmParser/
DX86AsmParser.cpp266 unsigned BaseReg, IndexReg, TmpReg, Scale; member in __anon6c2cceda0111::X86AsmParser::IntelExprStateMachine
276 State(IES_PLUS), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), TmpReg(0), in IntelExprStateMachine()
387 BaseReg = TmpReg; in onPlus()
390 IndexReg = TmpReg; in onPlus()
424 BaseReg = TmpReg; in onMinus()
427 IndexReg = TmpReg; in onMinus()
457 TmpReg = Reg; in onRegister()
514 IndexReg = TmpReg; in onInteger()
603 BaseReg = TmpReg; in onRBrac()
606 IndexReg = TmpReg; in onRBrac()
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/external/llvm/lib/Target/Mips/
DMipsSEInstrInfo.cpp568 unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg; in expandCvtFPInt() local
577 TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); in expandCvtFPInt()
582 BuildMI(MBB, I, DL, MovDesc, TmpReg).addReg(SrcReg, KillSrc); in expandCvtFPInt()
583 BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill); in expandCvtFPInt()
DMipsFastISel.cpp319 unsigned TmpReg = createResultReg(RC); in materialize32BitInt() local
320 emitInst(Mips::LUi, TmpReg).addImm(Hi); in materialize32BitInt()
321 emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo); in materialize32BitInt()
/external/llvm/lib/CodeGen/
DTwoAddressInstructionPass.cpp338 unsigned TmpReg = FromReg; in isRevCopyChain() local
340 MachineInstr *Def = getSingleDef(TmpReg, MBB, MRI); in isRevCopyChain()
344 TmpReg = Def->getOperand(1).getReg(); in isRevCopyChain()
346 if (TmpReg == ToReg) in isRevCopyChain()
/external/llvm/lib/Target/AArch64/
DAArch64FastISel.cpp380 unsigned TmpReg = createResultReg(RC); in materializeFP() local
381 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc1), TmpReg) in materializeFP()
387 .addReg(TmpReg, getKillRegState(true)); in materializeFP()
3969 unsigned TmpReg = MRI.createVirtualRegister(RC); in emitLSL_ri() local
3971 TII.get(AArch64::SUBREG_TO_REG), TmpReg) in emitLSL_ri()
3975 Op0 = TmpReg; in emitLSL_ri()
4090 unsigned TmpReg = MRI.createVirtualRegister(RC); in emitLSR_ri() local
4092 TII.get(AArch64::SUBREG_TO_REG), TmpReg) in emitLSR_ri()
4096 Op0 = TmpReg; in emitLSR_ri()
4199 unsigned TmpReg = MRI.createVirtualRegister(RC); in emitASR_ri() local
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/external/llvm/lib/Target/X86/
DX86FastISel.cpp1502 unsigned TmpReg = getRegForValue(BI->getCondition()); in X86SelectBranch() local
1503 if (TmpReg == 0) in X86SelectBranch()
1825 unsigned TmpReg = createResultReg(&X86::GR8RegClass); in X86FastEmitCMoveSelect() local
1826 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, TmpReg) in X86FastEmitCMoveSelect()
1837 unsigned TmpReg = getRegForValue(Cond); in X86FastEmitCMoveSelect() local
1838 if (TmpReg == 0) in X86FastEmitCMoveSelect()
DX86ISelLowering.cpp21215 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass); in EmitVAARG64WithCustomInserter() local
21218 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg) in EmitVAARG64WithCustomInserter()
21223 .addReg(TmpReg) in EmitVAARG64WithCustomInserter()
/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp3179 unsigned TmpReg = UpdReg; in expandAtomicRMW() local
3181 BuildMI(LoopMBB, DL, TII.get(SP::XORri), UpdReg).addReg(TmpReg).addImm(-1); in expandAtomicRMW()