1 /* 2 * V4L2 DV timings header. 3 * 4 * Copyright (C) 2012 Hans Verkuil <hans.verkuil@cisco.com> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * version 2 as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 18 * 02110-1301 USA 19 */ 20 21 #ifndef _V4L2_DV_TIMINGS_H 22 #define _V4L2_DV_TIMINGS_H 23 24 #if __GNUC__ < 4 || (__GNUC__ == 4 && (__GNUC_MINOR__ < 6)) 25 /* Sadly gcc versions older than 4.6 have a bug in how they initialize 26 anonymous unions where they require additional curly brackets. 27 This violates the C1x standard. This workaround adds the curly brackets 28 if needed. */ 29 #define V4L2_INIT_BT_TIMINGS(_width, args...) \ 30 { .bt = { _width , ## args } } 31 #else 32 #define V4L2_INIT_BT_TIMINGS(_width, args...) \ 33 .bt = { _width , ## args } 34 #endif 35 36 /* CEA-861-E timings (i.e. standard HDTV timings) */ 37 38 #define V4L2_DV_BT_CEA_640X480P59_94 { \ 39 .type = V4L2_DV_BT_656_1120, \ 40 V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \ 41 25175000, 16, 96, 48, 10, 2, 33, 0, 0, 0, \ 42 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, 0) \ 43 } 44 45 /* Note: these are the nominal timings, for HDMI links this format is typically 46 * double-clocked to meet the minimum pixelclock requirements. */ 47 #define V4L2_DV_BT_CEA_720X480I59_94 { \ 48 .type = V4L2_DV_BT_656_1120, \ 49 V4L2_INIT_BT_TIMINGS(720, 480, 1, 0, \ 50 13500000, 19, 62, 57, 4, 3, 15, 4, 3, 16, \ 51 V4L2_DV_BT_STD_CEA861, \ 52 V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO) \ 53 } 54 55 #define V4L2_DV_BT_CEA_720X480P59_94 { \ 56 .type = V4L2_DV_BT_656_1120, \ 57 V4L2_INIT_BT_TIMINGS(720, 480, 0, 0, \ 58 27000000, 16, 62, 60, 9, 6, 30, 0, 0, 0, \ 59 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \ 60 } 61 62 /* Note: these are the nominal timings, for HDMI links this format is typically 63 * double-clocked to meet the minimum pixelclock requirements. */ 64 #define V4L2_DV_BT_CEA_720X576I50 { \ 65 .type = V4L2_DV_BT_656_1120, \ 66 V4L2_INIT_BT_TIMINGS(720, 576, 1, 0, \ 67 13500000, 12, 63, 69, 2, 3, 19, 2, 3, 20, \ 68 V4L2_DV_BT_STD_CEA861, \ 69 V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO) \ 70 } 71 72 #define V4L2_DV_BT_CEA_720X576P50 { \ 73 .type = V4L2_DV_BT_656_1120, \ 74 V4L2_INIT_BT_TIMINGS(720, 576, 0, 0, \ 75 27000000, 12, 64, 68, 5, 5, 39, 0, 0, 0, \ 76 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \ 77 } 78 79 #define V4L2_DV_BT_CEA_1280X720P24 { \ 80 .type = V4L2_DV_BT_656_1120, \ 81 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \ 82 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 83 59400000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, \ 84 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \ 85 V4L2_DV_FL_CAN_REDUCE_FPS) \ 86 } 87 88 #define V4L2_DV_BT_CEA_1280X720P25 { \ 89 .type = V4L2_DV_BT_656_1120, \ 90 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \ 91 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 92 74250000, 2420, 40, 220, 5, 5, 20, 0, 0, 0, \ 93 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \ 94 } 95 96 #define V4L2_DV_BT_CEA_1280X720P30 { \ 97 .type = V4L2_DV_BT_656_1120, \ 98 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \ 99 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 100 74250000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, \ 101 V4L2_DV_BT_STD_CEA861, \ 102 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \ 103 } 104 105 #define V4L2_DV_BT_CEA_1280X720P50 { \ 106 .type = V4L2_DV_BT_656_1120, \ 107 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \ 108 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 109 74250000, 440, 40, 220, 5, 5, 20, 0, 0, 0, \ 110 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \ 111 } 112 113 #define V4L2_DV_BT_CEA_1280X720P60 { \ 114 .type = V4L2_DV_BT_656_1120, \ 115 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \ 116 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 117 74250000, 110, 40, 220, 5, 5, 20, 0, 0, 0, \ 118 V4L2_DV_BT_STD_CEA861, \ 119 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \ 120 } 121 122 #define V4L2_DV_BT_CEA_1920X1080P24 { \ 123 .type = V4L2_DV_BT_656_1120, \ 124 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \ 125 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 126 74250000, 638, 44, 148, 4, 5, 36, 0, 0, 0, \ 127 V4L2_DV_BT_STD_CEA861, \ 128 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \ 129 } 130 131 #define V4L2_DV_BT_CEA_1920X1080P25 { \ 132 .type = V4L2_DV_BT_656_1120, \ 133 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \ 134 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 135 74250000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \ 136 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \ 137 } 138 139 #define V4L2_DV_BT_CEA_1920X1080P30 { \ 140 .type = V4L2_DV_BT_656_1120, \ 141 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \ 142 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 143 74250000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \ 144 V4L2_DV_BT_STD_CEA861, \ 145 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \ 146 } 147 148 #define V4L2_DV_BT_CEA_1920X1080I50 { \ 149 .type = V4L2_DV_BT_656_1120, \ 150 V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \ 151 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 152 74250000, 528, 44, 148, 2, 5, 15, 2, 5, 16, \ 153 V4L2_DV_BT_STD_CEA861, \ 154 V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO) \ 155 } 156 157 #define V4L2_DV_BT_CEA_1920X1080P50 { \ 158 .type = V4L2_DV_BT_656_1120, \ 159 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \ 160 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 161 148500000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \ 162 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \ 163 } 164 165 #define V4L2_DV_BT_CEA_1920X1080I60 { \ 166 .type = V4L2_DV_BT_656_1120, \ 167 V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \ 168 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 169 74250000, 88, 44, 148, 2, 5, 15, 2, 5, 16, \ 170 V4L2_DV_BT_STD_CEA861, \ 171 V4L2_DV_FL_CAN_REDUCE_FPS | \ 172 V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO) \ 173 } 174 175 #define V4L2_DV_BT_CEA_1920X1080P60 { \ 176 .type = V4L2_DV_BT_656_1120, \ 177 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \ 178 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 179 148500000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \ 180 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \ 181 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \ 182 } 183 184 #define V4L2_DV_BT_CEA_3840X2160P24 { \ 185 .type = V4L2_DV_BT_656_1120, \ 186 V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \ 187 297000000, 1276, 88, 296, 8, 10, 72, 0, 0, 0, \ 188 V4L2_DV_BT_STD_CEA861, \ 189 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \ 190 } 191 192 #define V4L2_DV_BT_CEA_3840X2160P25 { \ 193 .type = V4L2_DV_BT_656_1120, \ 194 V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \ 195 297000000, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \ 196 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \ 197 } 198 199 #define V4L2_DV_BT_CEA_3840X2160P30 { \ 200 .type = V4L2_DV_BT_656_1120, \ 201 V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \ 202 297000000, 176, 88, 296, 8, 10, 72, 0, 0, 0, \ 203 V4L2_DV_BT_STD_CEA861, \ 204 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \ 205 } 206 207 #define V4L2_DV_BT_CEA_3840X2160P50 { \ 208 .type = V4L2_DV_BT_656_1120, \ 209 V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \ 210 594000000, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \ 211 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \ 212 } 213 214 #define V4L2_DV_BT_CEA_3840X2160P60 { \ 215 .type = V4L2_DV_BT_656_1120, \ 216 V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \ 217 594000000, 176, 88, 296, 8, 10, 72, 0, 0, 0, \ 218 V4L2_DV_BT_STD_CEA861, \ 219 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \ 220 } 221 222 #define V4L2_DV_BT_CEA_4096X2160P24 { \ 223 .type = V4L2_DV_BT_656_1120, \ 224 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \ 225 297000000, 1020, 88, 296, 8, 10, 72, 0, 0, 0, \ 226 V4L2_DV_BT_STD_CEA861, \ 227 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \ 228 } 229 230 #define V4L2_DV_BT_CEA_4096X2160P25 { \ 231 .type = V4L2_DV_BT_656_1120, \ 232 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \ 233 297000000, 968, 88, 128, 8, 10, 72, 0, 0, 0, \ 234 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \ 235 } 236 237 #define V4L2_DV_BT_CEA_4096X2160P30 { \ 238 .type = V4L2_DV_BT_656_1120, \ 239 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \ 240 297000000, 88, 88, 128, 8, 10, 72, 0, 0, 0, \ 241 V4L2_DV_BT_STD_CEA861, \ 242 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \ 243 } 244 245 #define V4L2_DV_BT_CEA_4096X2160P50 { \ 246 .type = V4L2_DV_BT_656_1120, \ 247 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \ 248 594000000, 968, 88, 128, 8, 10, 72, 0, 0, 0, \ 249 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \ 250 } 251 252 #define V4L2_DV_BT_CEA_4096X2160P60 { \ 253 .type = V4L2_DV_BT_656_1120, \ 254 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \ 255 594000000, 88, 88, 128, 8, 10, 72, 0, 0, 0, \ 256 V4L2_DV_BT_STD_CEA861, \ 257 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \ 258 } 259 260 261 /* VESA Discrete Monitor Timings as per version 1.0, revision 12 */ 262 263 #define V4L2_DV_BT_DMT_640X350P85 { \ 264 .type = V4L2_DV_BT_656_1120, \ 265 V4L2_INIT_BT_TIMINGS(640, 350, 0, V4L2_DV_HSYNC_POS_POL, \ 266 31500000, 32, 64, 96, 32, 3, 60, 0, 0, 0, \ 267 V4L2_DV_BT_STD_DMT, 0) \ 268 } 269 270 #define V4L2_DV_BT_DMT_640X400P85 { \ 271 .type = V4L2_DV_BT_656_1120, \ 272 V4L2_INIT_BT_TIMINGS(640, 400, 0, V4L2_DV_VSYNC_POS_POL, \ 273 31500000, 32, 64, 96, 1, 3, 41, 0, 0, 0, \ 274 V4L2_DV_BT_STD_DMT, 0) \ 275 } 276 277 #define V4L2_DV_BT_DMT_720X400P85 { \ 278 .type = V4L2_DV_BT_656_1120, \ 279 V4L2_INIT_BT_TIMINGS(720, 400, 0, V4L2_DV_VSYNC_POS_POL, \ 280 35500000, 36, 72, 108, 1, 3, 42, 0, 0, 0, \ 281 V4L2_DV_BT_STD_DMT, 0) \ 282 } 283 284 /* VGA resolutions */ 285 #define V4L2_DV_BT_DMT_640X480P60 V4L2_DV_BT_CEA_640X480P59_94 286 287 #define V4L2_DV_BT_DMT_640X480P72 { \ 288 .type = V4L2_DV_BT_656_1120, \ 289 V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \ 290 31500000, 24, 40, 128, 9, 3, 28, 0, 0, 0, \ 291 V4L2_DV_BT_STD_DMT, 0) \ 292 } 293 294 #define V4L2_DV_BT_DMT_640X480P75 { \ 295 .type = V4L2_DV_BT_656_1120, \ 296 V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \ 297 31500000, 16, 64, 120, 1, 3, 16, 0, 0, 0, \ 298 V4L2_DV_BT_STD_DMT, 0) \ 299 } 300 301 #define V4L2_DV_BT_DMT_640X480P85 { \ 302 .type = V4L2_DV_BT_656_1120, \ 303 V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \ 304 36000000, 56, 56, 80, 1, 3, 25, 0, 0, 0, \ 305 V4L2_DV_BT_STD_DMT, 0) \ 306 } 307 308 /* SVGA resolutions */ 309 #define V4L2_DV_BT_DMT_800X600P56 { \ 310 .type = V4L2_DV_BT_656_1120, \ 311 V4L2_INIT_BT_TIMINGS(800, 600, 0, \ 312 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 313 36000000, 24, 72, 128, 1, 2, 22, 0, 0, 0, \ 314 V4L2_DV_BT_STD_DMT, 0) \ 315 } 316 317 #define V4L2_DV_BT_DMT_800X600P60 { \ 318 .type = V4L2_DV_BT_656_1120, \ 319 V4L2_INIT_BT_TIMINGS(800, 600, 0, \ 320 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 321 40000000, 40, 128, 88, 1, 4, 23, 0, 0, 0, \ 322 V4L2_DV_BT_STD_DMT, 0) \ 323 } 324 325 #define V4L2_DV_BT_DMT_800X600P72 { \ 326 .type = V4L2_DV_BT_656_1120, \ 327 V4L2_INIT_BT_TIMINGS(800, 600, 0, \ 328 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 329 50000000, 56, 120, 64, 37, 6, 23, 0, 0, 0, \ 330 V4L2_DV_BT_STD_DMT, 0) \ 331 } 332 333 #define V4L2_DV_BT_DMT_800X600P75 { \ 334 .type = V4L2_DV_BT_656_1120, \ 335 V4L2_INIT_BT_TIMINGS(800, 600, 0, \ 336 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 337 49500000, 16, 80, 160, 1, 3, 21, 0, 0, 0, \ 338 V4L2_DV_BT_STD_DMT, 0) \ 339 } 340 341 #define V4L2_DV_BT_DMT_800X600P85 { \ 342 .type = V4L2_DV_BT_656_1120, \ 343 V4L2_INIT_BT_TIMINGS(800, 600, 0, \ 344 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 345 56250000, 32, 64, 152, 1, 3, 27, 0, 0, 0, \ 346 V4L2_DV_BT_STD_DMT, 0) \ 347 } 348 349 #define V4L2_DV_BT_DMT_800X600P120_RB { \ 350 .type = V4L2_DV_BT_656_1120, \ 351 V4L2_INIT_BT_TIMINGS(800, 600, 0, V4L2_DV_HSYNC_POS_POL, \ 352 73250000, 48, 32, 80, 3, 4, 29, 0, 0, 0, \ 353 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 354 V4L2_DV_FL_REDUCED_BLANKING) \ 355 } 356 357 #define V4L2_DV_BT_DMT_848X480P60 { \ 358 .type = V4L2_DV_BT_656_1120, \ 359 V4L2_INIT_BT_TIMINGS(848, 480, 0, \ 360 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 361 33750000, 16, 112, 112, 6, 8, 23, 0, 0, 0, \ 362 V4L2_DV_BT_STD_DMT, 0) \ 363 } 364 365 #define V4L2_DV_BT_DMT_1024X768I43 { \ 366 .type = V4L2_DV_BT_656_1120, \ 367 V4L2_INIT_BT_TIMINGS(1024, 768, 1, \ 368 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 369 44900000, 8, 176, 56, 0, 4, 20, 0, 4, 21, \ 370 V4L2_DV_BT_STD_DMT, 0) \ 371 } 372 373 /* XGA resolutions */ 374 #define V4L2_DV_BT_DMT_1024X768P60 { \ 375 .type = V4L2_DV_BT_656_1120, \ 376 V4L2_INIT_BT_TIMINGS(1024, 768, 0, 0, \ 377 65000000, 24, 136, 160, 3, 6, 29, 0, 0, 0, \ 378 V4L2_DV_BT_STD_DMT, 0) \ 379 } 380 381 #define V4L2_DV_BT_DMT_1024X768P70 { \ 382 .type = V4L2_DV_BT_656_1120, \ 383 V4L2_INIT_BT_TIMINGS(1024, 768, 0, 0, \ 384 75000000, 24, 136, 144, 3, 6, 29, 0, 0, 0, \ 385 V4L2_DV_BT_STD_DMT, 0) \ 386 } 387 388 #define V4L2_DV_BT_DMT_1024X768P75 { \ 389 .type = V4L2_DV_BT_656_1120, \ 390 V4L2_INIT_BT_TIMINGS(1024, 768, 0, \ 391 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 392 78750000, 16, 96, 176, 1, 3, 28, 0, 0, 0, \ 393 V4L2_DV_BT_STD_DMT, 0) \ 394 } 395 396 #define V4L2_DV_BT_DMT_1024X768P85 { \ 397 .type = V4L2_DV_BT_656_1120, \ 398 V4L2_INIT_BT_TIMINGS(1024, 768, 0, \ 399 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 400 94500000, 48, 96, 208, 1, 3, 36, 0, 0, 0, \ 401 V4L2_DV_BT_STD_DMT, 0) \ 402 } 403 404 #define V4L2_DV_BT_DMT_1024X768P120_RB { \ 405 .type = V4L2_DV_BT_656_1120, \ 406 V4L2_INIT_BT_TIMINGS(1024, 768, 0, V4L2_DV_HSYNC_POS_POL, \ 407 115500000, 48, 32, 80, 3, 4, 38, 0, 0, 0, \ 408 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 409 V4L2_DV_FL_REDUCED_BLANKING) \ 410 } 411 412 /* XGA+ resolution */ 413 #define V4L2_DV_BT_DMT_1152X864P75 { \ 414 .type = V4L2_DV_BT_656_1120, \ 415 V4L2_INIT_BT_TIMINGS(1152, 864, 0, \ 416 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 417 108000000, 64, 128, 256, 1, 3, 32, 0, 0, 0, \ 418 V4L2_DV_BT_STD_DMT, 0) \ 419 } 420 421 #define V4L2_DV_BT_DMT_1280X720P60 V4L2_DV_BT_CEA_1280X720P60 422 423 /* WXGA resolutions */ 424 #define V4L2_DV_BT_DMT_1280X768P60_RB { \ 425 .type = V4L2_DV_BT_656_1120, \ 426 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_HSYNC_POS_POL, \ 427 68250000, 48, 32, 80, 3, 7, 12, 0, 0, 0, \ 428 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 429 V4L2_DV_FL_REDUCED_BLANKING) \ 430 } 431 432 #define V4L2_DV_BT_DMT_1280X768P60 { \ 433 .type = V4L2_DV_BT_656_1120, \ 434 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \ 435 79500000, 64, 128, 192, 3, 7, 20, 0, 0, 0, \ 436 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 437 } 438 439 #define V4L2_DV_BT_DMT_1280X768P75 { \ 440 .type = V4L2_DV_BT_656_1120, \ 441 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \ 442 102250000, 80, 128, 208, 3, 7, 27, 0, 0, 0, \ 443 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 444 } 445 446 #define V4L2_DV_BT_DMT_1280X768P85 { \ 447 .type = V4L2_DV_BT_656_1120, \ 448 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \ 449 117500000, 80, 136, 216, 3, 7, 31, 0, 0, 0, \ 450 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 451 } 452 453 #define V4L2_DV_BT_DMT_1280X768P120_RB { \ 454 .type = V4L2_DV_BT_656_1120, \ 455 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_HSYNC_POS_POL, \ 456 140250000, 48, 32, 80, 3, 7, 35, 0, 0, 0, \ 457 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 458 V4L2_DV_FL_REDUCED_BLANKING) \ 459 } 460 461 #define V4L2_DV_BT_DMT_1280X800P60_RB { \ 462 .type = V4L2_DV_BT_656_1120, \ 463 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, \ 464 71000000, 48, 32, 80, 3, 6, 14, 0, 0, 0, \ 465 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 466 V4L2_DV_FL_REDUCED_BLANKING) \ 467 } 468 469 #define V4L2_DV_BT_DMT_1280X800P60 { \ 470 .type = V4L2_DV_BT_656_1120, \ 471 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \ 472 83500000, 72, 128, 200, 3, 6, 22, 0, 0, 0, \ 473 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 474 } 475 476 #define V4L2_DV_BT_DMT_1280X800P75 { \ 477 .type = V4L2_DV_BT_656_1120, \ 478 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \ 479 106500000, 80, 128, 208, 3, 6, 29, 0, 0, 0, \ 480 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 481 } 482 483 #define V4L2_DV_BT_DMT_1280X800P85 { \ 484 .type = V4L2_DV_BT_656_1120, \ 485 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \ 486 122500000, 80, 136, 216, 3, 6, 34, 0, 0, 0, \ 487 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 488 } 489 490 #define V4L2_DV_BT_DMT_1280X800P120_RB { \ 491 .type = V4L2_DV_BT_656_1120, \ 492 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, \ 493 146250000, 48, 32, 80, 3, 6, 38, 0, 0, 0, \ 494 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 495 V4L2_DV_FL_REDUCED_BLANKING) \ 496 } 497 498 #define V4L2_DV_BT_DMT_1280X960P60 { \ 499 .type = V4L2_DV_BT_656_1120, \ 500 V4L2_INIT_BT_TIMINGS(1280, 960, 0, \ 501 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 502 108000000, 96, 112, 312, 1, 3, 36, 0, 0, 0, \ 503 V4L2_DV_BT_STD_DMT, 0) \ 504 } 505 506 #define V4L2_DV_BT_DMT_1280X960P85 { \ 507 .type = V4L2_DV_BT_656_1120, \ 508 V4L2_INIT_BT_TIMINGS(1280, 960, 0, \ 509 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 510 148500000, 64, 160, 224, 1, 3, 47, 0, 0, 0, \ 511 V4L2_DV_BT_STD_DMT, 0) \ 512 } 513 514 #define V4L2_DV_BT_DMT_1280X960P120_RB { \ 515 .type = V4L2_DV_BT_656_1120, \ 516 V4L2_INIT_BT_TIMINGS(1280, 960, 0, V4L2_DV_HSYNC_POS_POL, \ 517 175500000, 48, 32, 80, 3, 4, 50, 0, 0, 0, \ 518 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 519 V4L2_DV_FL_REDUCED_BLANKING) \ 520 } 521 522 /* SXGA resolutions */ 523 #define V4L2_DV_BT_DMT_1280X1024P60 { \ 524 .type = V4L2_DV_BT_656_1120, \ 525 V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \ 526 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 527 108000000, 48, 112, 248, 1, 3, 38, 0, 0, 0, \ 528 V4L2_DV_BT_STD_DMT, 0) \ 529 } 530 531 #define V4L2_DV_BT_DMT_1280X1024P75 { \ 532 .type = V4L2_DV_BT_656_1120, \ 533 V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \ 534 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 535 135000000, 16, 144, 248, 1, 3, 38, 0, 0, 0, \ 536 V4L2_DV_BT_STD_DMT, 0) \ 537 } 538 539 #define V4L2_DV_BT_DMT_1280X1024P85 { \ 540 .type = V4L2_DV_BT_656_1120, \ 541 V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \ 542 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 543 157500000, 64, 160, 224, 1, 3, 44, 0, 0, 0, \ 544 V4L2_DV_BT_STD_DMT, 0) \ 545 } 546 547 #define V4L2_DV_BT_DMT_1280X1024P120_RB { \ 548 .type = V4L2_DV_BT_656_1120, \ 549 V4L2_INIT_BT_TIMINGS(1280, 1024, 0, V4L2_DV_HSYNC_POS_POL, \ 550 187250000, 48, 32, 80, 3, 7, 50, 0, 0, 0, \ 551 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 552 V4L2_DV_FL_REDUCED_BLANKING) \ 553 } 554 555 #define V4L2_DV_BT_DMT_1360X768P60 { \ 556 .type = V4L2_DV_BT_656_1120, \ 557 V4L2_INIT_BT_TIMINGS(1360, 768, 0, \ 558 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 559 85500000, 64, 112, 256, 3, 6, 18, 0, 0, 0, \ 560 V4L2_DV_BT_STD_DMT, 0) \ 561 } 562 563 #define V4L2_DV_BT_DMT_1360X768P120_RB { \ 564 .type = V4L2_DV_BT_656_1120, \ 565 V4L2_INIT_BT_TIMINGS(1360, 768, 0, V4L2_DV_HSYNC_POS_POL, \ 566 148250000, 48, 32, 80, 3, 5, 37, 0, 0, 0, \ 567 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 568 V4L2_DV_FL_REDUCED_BLANKING) \ 569 } 570 571 #define V4L2_DV_BT_DMT_1366X768P60 { \ 572 .type = V4L2_DV_BT_656_1120, \ 573 V4L2_INIT_BT_TIMINGS(1366, 768, 0, \ 574 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 575 85500000, 70, 143, 213, 3, 3, 24, 0, 0, 0, \ 576 V4L2_DV_BT_STD_DMT, 0) \ 577 } 578 579 #define V4L2_DV_BT_DMT_1366X768P60_RB { \ 580 .type = V4L2_DV_BT_656_1120, \ 581 V4L2_INIT_BT_TIMINGS(1366, 768, 0, \ 582 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 583 72000000, 14, 56, 64, 1, 3, 28, 0, 0, 0, \ 584 V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \ 585 } 586 587 /* SXGA+ resolutions */ 588 #define V4L2_DV_BT_DMT_1400X1050P60_RB { \ 589 .type = V4L2_DV_BT_656_1120, \ 590 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_HSYNC_POS_POL, \ 591 101000000, 48, 32, 80, 3, 4, 23, 0, 0, 0, \ 592 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 593 V4L2_DV_FL_REDUCED_BLANKING) \ 594 } 595 596 #define V4L2_DV_BT_DMT_1400X1050P60 { \ 597 .type = V4L2_DV_BT_656_1120, \ 598 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \ 599 121750000, 88, 144, 232, 3, 4, 32, 0, 0, 0, \ 600 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 601 } 602 603 #define V4L2_DV_BT_DMT_1400X1050P75 { \ 604 .type = V4L2_DV_BT_656_1120, \ 605 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \ 606 156000000, 104, 144, 248, 3, 4, 42, 0, 0, 0, \ 607 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 608 } 609 610 #define V4L2_DV_BT_DMT_1400X1050P85 { \ 611 .type = V4L2_DV_BT_656_1120, \ 612 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \ 613 179500000, 104, 152, 256, 3, 4, 48, 0, 0, 0, \ 614 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 615 } 616 617 #define V4L2_DV_BT_DMT_1400X1050P120_RB { \ 618 .type = V4L2_DV_BT_656_1120, \ 619 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_HSYNC_POS_POL, \ 620 208000000, 48, 32, 80, 3, 4, 55, 0, 0, 0, \ 621 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 622 V4L2_DV_FL_REDUCED_BLANKING) \ 623 } 624 625 /* WXGA+ resolutions */ 626 #define V4L2_DV_BT_DMT_1440X900P60_RB { \ 627 .type = V4L2_DV_BT_656_1120, \ 628 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_HSYNC_POS_POL, \ 629 88750000, 48, 32, 80, 3, 6, 17, 0, 0, 0, \ 630 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 631 V4L2_DV_FL_REDUCED_BLANKING) \ 632 } 633 634 #define V4L2_DV_BT_DMT_1440X900P60 { \ 635 .type = V4L2_DV_BT_656_1120, \ 636 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \ 637 106500000, 80, 152, 232, 3, 6, 25, 0, 0, 0, \ 638 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 639 } 640 641 #define V4L2_DV_BT_DMT_1440X900P75 { \ 642 .type = V4L2_DV_BT_656_1120, \ 643 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \ 644 136750000, 96, 152, 248, 3, 6, 33, 0, 0, 0, \ 645 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 646 } 647 648 #define V4L2_DV_BT_DMT_1440X900P85 { \ 649 .type = V4L2_DV_BT_656_1120, \ 650 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \ 651 157000000, 104, 152, 256, 3, 6, 39, 0, 0, 0, \ 652 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 653 } 654 655 #define V4L2_DV_BT_DMT_1440X900P120_RB { \ 656 .type = V4L2_DV_BT_656_1120, \ 657 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_HSYNC_POS_POL, \ 658 182750000, 48, 32, 80, 3, 6, 44, 0, 0, 0, \ 659 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 660 V4L2_DV_FL_REDUCED_BLANKING) \ 661 } 662 663 #define V4L2_DV_BT_DMT_1600X900P60_RB { \ 664 .type = V4L2_DV_BT_656_1120, \ 665 V4L2_INIT_BT_TIMINGS(1600, 900, 0, \ 666 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 667 108000000, 24, 80, 96, 1, 3, 96, 0, 0, 0, \ 668 V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \ 669 } 670 671 /* UXGA resolutions */ 672 #define V4L2_DV_BT_DMT_1600X1200P60 { \ 673 .type = V4L2_DV_BT_656_1120, \ 674 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \ 675 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 676 162000000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \ 677 V4L2_DV_BT_STD_DMT, 0) \ 678 } 679 680 #define V4L2_DV_BT_DMT_1600X1200P65 { \ 681 .type = V4L2_DV_BT_656_1120, \ 682 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \ 683 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 684 175500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \ 685 V4L2_DV_BT_STD_DMT, 0) \ 686 } 687 688 #define V4L2_DV_BT_DMT_1600X1200P70 { \ 689 .type = V4L2_DV_BT_656_1120, \ 690 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \ 691 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 692 189000000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \ 693 V4L2_DV_BT_STD_DMT, 0) \ 694 } 695 696 #define V4L2_DV_BT_DMT_1600X1200P75 { \ 697 .type = V4L2_DV_BT_656_1120, \ 698 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \ 699 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 700 202500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \ 701 V4L2_DV_BT_STD_DMT, 0) \ 702 } 703 704 #define V4L2_DV_BT_DMT_1600X1200P85 { \ 705 .type = V4L2_DV_BT_656_1120, \ 706 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \ 707 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 708 229500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \ 709 V4L2_DV_BT_STD_DMT, 0) \ 710 } 711 712 #define V4L2_DV_BT_DMT_1600X1200P120_RB { \ 713 .type = V4L2_DV_BT_656_1120, \ 714 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, V4L2_DV_HSYNC_POS_POL, \ 715 268250000, 48, 32, 80, 3, 4, 64, 0, 0, 0, \ 716 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 717 V4L2_DV_FL_REDUCED_BLANKING) \ 718 } 719 720 /* WSXGA+ resolutions */ 721 #define V4L2_DV_BT_DMT_1680X1050P60_RB { \ 722 .type = V4L2_DV_BT_656_1120, \ 723 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_HSYNC_POS_POL, \ 724 119000000, 48, 32, 80, 3, 6, 21, 0, 0, 0, \ 725 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 726 V4L2_DV_FL_REDUCED_BLANKING) \ 727 } 728 729 #define V4L2_DV_BT_DMT_1680X1050P60 { \ 730 .type = V4L2_DV_BT_656_1120, \ 731 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \ 732 146250000, 104, 176, 280, 3, 6, 30, 0, 0, 0, \ 733 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 734 } 735 736 #define V4L2_DV_BT_DMT_1680X1050P75 { \ 737 .type = V4L2_DV_BT_656_1120, \ 738 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \ 739 187000000, 120, 176, 296, 3, 6, 40, 0, 0, 0, \ 740 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 741 } 742 743 #define V4L2_DV_BT_DMT_1680X1050P85 { \ 744 .type = V4L2_DV_BT_656_1120, \ 745 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \ 746 214750000, 128, 176, 304, 3, 6, 46, 0, 0, 0, \ 747 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 748 } 749 750 #define V4L2_DV_BT_DMT_1680X1050P120_RB { \ 751 .type = V4L2_DV_BT_656_1120, \ 752 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_HSYNC_POS_POL, \ 753 245500000, 48, 32, 80, 3, 6, 53, 0, 0, 0, \ 754 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 755 V4L2_DV_FL_REDUCED_BLANKING) \ 756 } 757 758 #define V4L2_DV_BT_DMT_1792X1344P60 { \ 759 .type = V4L2_DV_BT_656_1120, \ 760 V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \ 761 204750000, 128, 200, 328, 1, 3, 46, 0, 0, 0, \ 762 V4L2_DV_BT_STD_DMT, 0) \ 763 } 764 765 #define V4L2_DV_BT_DMT_1792X1344P75 { \ 766 .type = V4L2_DV_BT_656_1120, \ 767 V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \ 768 261000000, 96, 216, 352, 1, 3, 69, 0, 0, 0, \ 769 V4L2_DV_BT_STD_DMT, 0) \ 770 } 771 772 #define V4L2_DV_BT_DMT_1792X1344P120_RB { \ 773 .type = V4L2_DV_BT_656_1120, \ 774 V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_HSYNC_POS_POL, \ 775 333250000, 48, 32, 80, 3, 4, 72, 0, 0, 0, \ 776 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 777 V4L2_DV_FL_REDUCED_BLANKING) \ 778 } 779 780 #define V4L2_DV_BT_DMT_1856X1392P60 { \ 781 .type = V4L2_DV_BT_656_1120, \ 782 V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \ 783 218250000, 96, 224, 352, 1, 3, 43, 0, 0, 0, \ 784 V4L2_DV_BT_STD_DMT, 0) \ 785 } 786 787 #define V4L2_DV_BT_DMT_1856X1392P75 { \ 788 .type = V4L2_DV_BT_656_1120, \ 789 V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \ 790 288000000, 128, 224, 352, 1, 3, 104, 0, 0, 0, \ 791 V4L2_DV_BT_STD_DMT, 0) \ 792 } 793 794 #define V4L2_DV_BT_DMT_1856X1392P120_RB { \ 795 .type = V4L2_DV_BT_656_1120, \ 796 V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_HSYNC_POS_POL, \ 797 356500000, 48, 32, 80, 3, 4, 75, 0, 0, 0, \ 798 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 799 V4L2_DV_FL_REDUCED_BLANKING) \ 800 } 801 802 #define V4L2_DV_BT_DMT_1920X1080P60 V4L2_DV_BT_CEA_1920X1080P60 803 804 /* WUXGA resolutions */ 805 #define V4L2_DV_BT_DMT_1920X1200P60_RB { \ 806 .type = V4L2_DV_BT_656_1120, \ 807 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_HSYNC_POS_POL, \ 808 154000000, 48, 32, 80, 3, 6, 26, 0, 0, 0, \ 809 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 810 V4L2_DV_FL_REDUCED_BLANKING) \ 811 } 812 813 #define V4L2_DV_BT_DMT_1920X1200P60 { \ 814 .type = V4L2_DV_BT_656_1120, \ 815 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \ 816 193250000, 136, 200, 336, 3, 6, 36, 0, 0, 0, \ 817 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 818 } 819 820 #define V4L2_DV_BT_DMT_1920X1200P75 { \ 821 .type = V4L2_DV_BT_656_1120, \ 822 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \ 823 245250000, 136, 208, 344, 3, 6, 46, 0, 0, 0, \ 824 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 825 } 826 827 #define V4L2_DV_BT_DMT_1920X1200P85 { \ 828 .type = V4L2_DV_BT_656_1120, \ 829 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \ 830 281250000, 144, 208, 352, 3, 6, 53, 0, 0, 0, \ 831 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 832 } 833 834 #define V4L2_DV_BT_DMT_1920X1200P120_RB { \ 835 .type = V4L2_DV_BT_656_1120, \ 836 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_HSYNC_POS_POL, \ 837 317000000, 48, 32, 80, 3, 6, 62, 0, 0, 0, \ 838 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 839 V4L2_DV_FL_REDUCED_BLANKING) \ 840 } 841 842 #define V4L2_DV_BT_DMT_1920X1440P60 { \ 843 .type = V4L2_DV_BT_656_1120, \ 844 V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \ 845 234000000, 128, 208, 344, 1, 3, 56, 0, 0, 0, \ 846 V4L2_DV_BT_STD_DMT, 0) \ 847 } 848 849 #define V4L2_DV_BT_DMT_1920X1440P75 { \ 850 .type = V4L2_DV_BT_656_1120, \ 851 V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \ 852 297000000, 144, 224, 352, 1, 3, 56, 0, 0, 0, \ 853 V4L2_DV_BT_STD_DMT, 0) \ 854 } 855 856 #define V4L2_DV_BT_DMT_1920X1440P120_RB { \ 857 .type = V4L2_DV_BT_656_1120, \ 858 V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_HSYNC_POS_POL, \ 859 380500000, 48, 32, 80, 3, 4, 78, 0, 0, 0, \ 860 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 861 V4L2_DV_FL_REDUCED_BLANKING) \ 862 } 863 864 #define V4L2_DV_BT_DMT_2048X1152P60_RB { \ 865 .type = V4L2_DV_BT_656_1120, \ 866 V4L2_INIT_BT_TIMINGS(2048, 1152, 0, \ 867 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 868 162000000, 26, 80, 96, 1, 3, 44, 0, 0, 0, \ 869 V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \ 870 } 871 872 /* WQXGA resolutions */ 873 #define V4L2_DV_BT_DMT_2560X1600P60_RB { \ 874 .type = V4L2_DV_BT_656_1120, \ 875 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_HSYNC_POS_POL, \ 876 268500000, 48, 32, 80, 3, 6, 37, 0, 0, 0, \ 877 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 878 V4L2_DV_FL_REDUCED_BLANKING) \ 879 } 880 881 #define V4L2_DV_BT_DMT_2560X1600P60 { \ 882 .type = V4L2_DV_BT_656_1120, \ 883 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \ 884 348500000, 192, 280, 472, 3, 6, 49, 0, 0, 0, \ 885 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 886 } 887 888 #define V4L2_DV_BT_DMT_2560X1600P75 { \ 889 .type = V4L2_DV_BT_656_1120, \ 890 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \ 891 443250000, 208, 280, 488, 3, 6, 63, 0, 0, 0, \ 892 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 893 } 894 895 #define V4L2_DV_BT_DMT_2560X1600P85 { \ 896 .type = V4L2_DV_BT_656_1120, \ 897 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \ 898 505250000, 208, 280, 488, 3, 6, 73, 0, 0, 0, \ 899 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ 900 } 901 902 #define V4L2_DV_BT_DMT_2560X1600P120_RB { \ 903 .type = V4L2_DV_BT_656_1120, \ 904 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_HSYNC_POS_POL, \ 905 552750000, 48, 32, 80, 3, 6, 85, 0, 0, 0, \ 906 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 907 V4L2_DV_FL_REDUCED_BLANKING) \ 908 } 909 910 /* 4K resolutions */ 911 #define V4L2_DV_BT_DMT_4096X2160P60_RB { \ 912 .type = V4L2_DV_BT_656_1120, \ 913 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \ 914 556744000, 8, 32, 40, 48, 8, 6, 0, 0, 0, \ 915 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 916 V4L2_DV_FL_REDUCED_BLANKING) \ 917 } 918 919 #define V4L2_DV_BT_DMT_4096X2160P59_94_RB { \ 920 .type = V4L2_DV_BT_656_1120, \ 921 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \ 922 556188000, 8, 32, 40, 48, 8, 6, 0, 0, 0, \ 923 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ 924 V4L2_DV_FL_REDUCED_BLANKING) \ 925 } 926 927 #endif 928