Searched refs:VLD4DUP (Results 1 – 4 of 4) sorted by relevance
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 193 VLD4DUP, enumerator
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| D | ARMInstrNEON.td | 1560 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
1561 class VLD4DUP<bits<4> op7_4, string Dt>
1571 def VLD4DUPd8 : VLD4DUP<{0,0,0,?}, "8">;
1572 def VLD4DUPd16 : VLD4DUP<{0,1,0,?}, "16">;
1573 def VLD4DUPd32 : VLD4DUP<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1580 def VLD4DUPq8 : VLD4DUP<{0,0,1,?}, "8">;
1581 def VLD4DUPq16 : VLD4DUP<{0,1,1,?}, "16">;
1582 def VLD4DUPq32 : VLD4DUP<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
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| D | ARMISelLowering.cpp | 1212 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP"; in getTargetNodeName()
9554 case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break; in CombineBaseUpdate()
9725 NewOpc = ARMISD::VLD4DUP; in CombineVLDDUP()
10600 case ARMISD::VLD4DUP: in PerformDAGCombine()
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| D | ARMISelDAGToDAG.cpp | 2858 case ARMISD::VLD4DUP: { in Select()
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