/external/llvm/lib/Target/Mips/Disassembler/ |
D | MipsDisassembler.cpp | 539 MI.addOperand(MCOperand::createImm(tmp)); in DecodeINSVE_DF() 545 MI.addOperand(MCOperand::createImm(0)); in DecodeINSVE_DF() 579 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch() 582 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch() 584 MI.addOperand(MCOperand::createImm(Imm)); in DecodeAddiGroupBranch() 618 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeDaddiGroupBranch() 621 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeDaddiGroupBranch() 623 MI.addOperand(MCOperand::createImm(Imm)); in DecodeDaddiGroupBranch() 660 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeBlezlGroupBranch() 663 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeBlezlGroupBranch() [all …]
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/external/llvm/lib/Target/ARM/AsmParser/ |
D | ARMAsmParser.cpp | 1676 Inst.addOperand(MCOperand::createImm(0)); in addExpr() 1678 Inst.addOperand(MCOperand::createImm(CE->getValue())); in addExpr() 1680 Inst.addOperand(MCOperand::createExpr(Expr)); in addExpr() 1685 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); in addCondCodeOperands() 1687 Inst.addOperand(MCOperand::createReg(RegNum)); in addCondCodeOperands() 1692 Inst.addOperand(MCOperand::createImm(getCoproc())); in addCoprocNumOperands() 1697 Inst.addOperand(MCOperand::createImm(getCoproc())); in addCoprocRegOperands() 1702 Inst.addOperand(MCOperand::createImm(CoprocOption.Val)); in addCoprocOptionOperands() 1707 Inst.addOperand(MCOperand::createImm(ITMask.Mask)); in addITMaskOperands() 1712 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); in addITCondCodeOperands() [all …]
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/external/llvm/lib/Target/PowerPC/AsmParser/ |
D | PPCAsmParser.cpp | 544 Inst.addOperand(MCOperand::createReg(RRegs[getReg()])); in addRegGPRCOperands() 549 Inst.addOperand(MCOperand::createReg(RRegsNoR0[getReg()])); in addRegGPRCNoR0Operands() 554 Inst.addOperand(MCOperand::createReg(XRegs[getReg()])); in addRegG8RCOperands() 559 Inst.addOperand(MCOperand::createReg(XRegsNoX0[getReg()])); in addRegG8RCNoX0Operands() 578 Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); in addRegF4RCOperands() 583 Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); in addRegF8RCOperands() 588 Inst.addOperand(MCOperand::createReg(VRegs[getReg()])); in addRegVRRCOperands() 593 Inst.addOperand(MCOperand::createReg(VSRegs[getVSReg()])); in addRegVSRCOperands() 598 Inst.addOperand(MCOperand::createReg(VSFRegs[getVSReg()])); in addRegVSFRCOperands() 603 Inst.addOperand(MCOperand::createReg(VSSRegs[getVSReg()])); in addRegVSSRCOperands() [all …]
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/external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
D | HexagonMCCompound.cpp | 222 CompoundInsn->addOperand(Rt); in getCompoundInsn() 223 CompoundInsn->addOperand(L.getOperand(1)); // Immediate in getCompoundInsn() 224 CompoundInsn->addOperand(R.getOperand(0)); // Jump target in getCompoundInsn() 234 CompoundInsn->addOperand(Rt); in getCompoundInsn() 235 CompoundInsn->addOperand(Rs); in getCompoundInsn() 236 CompoundInsn->addOperand(R.getOperand(0)); // Jump target. in getCompoundInsn() 248 CompoundInsn->addOperand(Rs); in getCompoundInsn() 249 CompoundInsn->addOperand(Rt); in getCompoundInsn() 250 CompoundInsn->addOperand(R.getOperand(1)); in getCompoundInsn() 261 CompoundInsn->addOperand(Rs); in getCompoundInsn() [all …]
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/external/mesa3d/src/gallium/drivers/radeon/ |
D | R600ISelLowering.cpp | 66 .addOperand(MI->getOperand(0)) in EmitInstrWithCustomInserter() 67 .addOperand(MI->getOperand(1)) in EmitInstrWithCustomInserter() 77 .addOperand(MI->getOperand(0)) in EmitInstrWithCustomInserter() 78 .addOperand(MI->getOperand(1)) in EmitInstrWithCustomInserter() 89 .addOperand(MI->getOperand(0)) in EmitInstrWithCustomInserter() 90 .addOperand(MI->getOperand(1)) in EmitInstrWithCustomInserter() 102 .addOperand(MI->getOperand(0)) in EmitInstrWithCustomInserter() 135 .addOperand(MI->getOperand(1)) in EmitInstrWithCustomInserter() 139 .addOperand(MI->getOperand(0)) in EmitInstrWithCustomInserter() 161 .addOperand(MI->getOperand(3)) in EmitInstrWithCustomInserter() [all …]
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D | SIISelLowering.cpp | 83 .addOperand(MI->getOperand(0)) in EmitInstrWithCustomInserter() 84 .addOperand(MI->getOperand(1)) in EmitInstrWithCustomInserter() 87 .addOperand(MI->getOperand(1)) in EmitInstrWithCustomInserter() 88 .addOperand(MI->getOperand(1)) in EmitInstrWithCustomInserter() 98 .addOperand(MI->getOperand(0)) in EmitInstrWithCustomInserter() 99 .addOperand(MI->getOperand(1)) in EmitInstrWithCustomInserter() 102 .addOperand(MI->getOperand(1)) in EmitInstrWithCustomInserter() 103 .addOperand(MI->getOperand(1)) in EmitInstrWithCustomInserter() 113 .addOperand(MI->getOperand(0)) in EmitInstrWithCustomInserter() 114 .addOperand(MI->getOperand(1)) in EmitInstrWithCustomInserter() [all …]
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/external/llvm/include/llvm/MC/ |
D | MCInstBuilder.h | 33 Inst.addOperand(MCOperand::createReg(Reg)); in addReg() 39 Inst.addOperand(MCOperand::createImm(Val)); in addImm() 45 Inst.addOperand(MCOperand::createFPImm(Val)); in addFPImm() 51 Inst.addOperand(MCOperand::createExpr(Val)); in addExpr() 57 Inst.addOperand(MCOperand::createInst(Val)); in addInst() 62 MCInstBuilder &addOperand(const MCOperand &Op) { in addOperand() function 63 Inst.addOperand(Op); in addOperand()
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/external/llvm/lib/Target/Hexagon/ |
D | HexagonAsmPrinter.cpp | 280 TmpInst.addOperand(Reg); in HexagonProcessInstruction() 281 TmpInst.addOperand(MCOperand::createExpr( in HexagonProcessInstruction() 299 TmpInst.addOperand(Reg); in HexagonProcessInstruction() 300 TmpInst.addOperand(MCOperand::createExpr( in HexagonProcessInstruction() 312 MappedInst.addOperand(Ps); in HexagonProcessInstruction() 374 TmpInst.addOperand(MappedInst.getOperand(0)); in HexagonProcessInstruction() 375 TmpInst.addOperand(MappedInst.getOperand(1)); in HexagonProcessInstruction() 380 TmpInst.addOperand(MappedInst.getOperand(0)); in HexagonProcessInstruction() 381 TmpInst.addOperand(MappedInst.getOperand(1)); in HexagonProcessInstruction() 384 TmpInst.addOperand(MCOperand::createExpr(Sub)); in HexagonProcessInstruction() [all …]
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D | HexagonExpandPredSpillCode.cpp | 108 Hexagon::C6)->addOperand(Op3); in runOnMachineFunction() 112 NewMI->addOperand(Op0); in runOnMachineFunction() 113 NewMI->addOperand(Op1); in runOnMachineFunction() 114 NewMI->addOperand(Op4); in runOnMachineFunction() 115 NewMI->addOperand(MachineOperand::CreateReg(Hexagon::M0, in runOnMachineFunction() 119 NewMI->addOperand(Op2); in runOnMachineFunction() 151 Hexagon::C6)->addOperand(Op4); in runOnMachineFunction() 155 NewMI->addOperand(Op1); in runOnMachineFunction() 156 NewMI->addOperand(Op0); in runOnMachineFunction() 157 NewMI->addOperand(Op2); in runOnMachineFunction() [all …]
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/external/llvm/lib/Target/SystemZ/Disassembler/ |
D | SystemZDisassembler.cpp | 55 Inst.addOperand(MCOperand::createReg(RegNo)); in decodeRegisterClass() 129 Inst.addOperand(MCOperand::createImm(Imm)); in decodeUImmOperand() 137 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm))); in decodeSImmOperand() 211 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm) * 2 + Address)); in decodePCDBLOperand() 232 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr12Operand() 233 Inst.addOperand(MCOperand::createImm(Disp)); in decodeBDAddr12Operand() 242 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr20Operand() 243 Inst.addOperand(MCOperand::createImm(SignExtend64<20>(Disp))); in decodeBDAddr20Operand() 253 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDXAddr12Operand() 254 Inst.addOperand(MCOperand::createImm(Disp)); in decodeBDXAddr12Operand() [all …]
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/external/llvm/lib/Target/Mips/MCTargetDesc/ |
D | MipsTargetStreamer.cpp | 762 TmpInst.addOperand(MCOperand::createReg(Mips::GP)); in emitDirectiveCpLoad() 765 TmpInst.addOperand(MCOperand::createExpr(HiSym)); in emitDirectiveCpLoad() 771 TmpInst.addOperand(MCOperand::createReg(Mips::GP)); in emitDirectiveCpLoad() 772 TmpInst.addOperand(MCOperand::createReg(Mips::GP)); in emitDirectiveCpLoad() 775 TmpInst.addOperand(MCOperand::createExpr(LoSym)); in emitDirectiveCpLoad() 781 TmpInst.addOperand(MCOperand::createReg(Mips::GP)); in emitDirectiveCpLoad() 782 TmpInst.addOperand(MCOperand::createReg(Mips::GP)); in emitDirectiveCpLoad() 783 TmpInst.addOperand(MCOperand::createReg(RegNo)); in emitDirectiveCpLoad() 822 Inst.addOperand(MCOperand::createReg(RegOrOffset)); in emitDirectiveCpsetup() 823 Inst.addOperand(MCOperand::createReg(Mips::GP)); in emitDirectiveCpsetup() [all …]
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/external/llvm/lib/Target/ARM/ |
D | ARMInstrInfo.cpp | 39 NopInst.addOperand(MCOperand::createImm(0)); in getNoopForMachoTarget() 40 NopInst.addOperand(MCOperand::createImm(ARMCC::AL)); in getNoopForMachoTarget() 41 NopInst.addOperand(MCOperand::createReg(0)); in getNoopForMachoTarget() 44 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNoopForMachoTarget() 45 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNoopForMachoTarget() 46 NopInst.addOperand(MCOperand::createImm(ARMCC::AL)); in getNoopForMachoTarget() 47 NopInst.addOperand(MCOperand::createReg(0)); in getNoopForMachoTarget() 48 NopInst.addOperand(MCOperand::createReg(0)); in getNoopForMachoTarget()
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D | ARMExpandPseudoInsts.cpp | 85 UseMI.addOperand(MO); in TransferImpOps() 87 DefMI.addOperand(MO); in TransferImpOps() 403 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD() 406 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD() 407 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD() 410 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD() 420 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD() 421 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD() 428 MIB.addOperand(MO); in ExpandVLD() 455 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVST() [all …]
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/external/llvm/include/llvm/CodeGen/ |
D | MachineInstrBuilder.h | 69 MI->addOperand(*MF, MachineOperand::CreateReg(RegNo, 84 MI->addOperand(*MF, MachineOperand::CreateImm(Val)); in addImm() 89 MI->addOperand(*MF, MachineOperand::CreateCImm(Val)); in addCImm() 94 MI->addOperand(*MF, MachineOperand::CreateFPImm(Val)); in addFPImm() 100 MI->addOperand(*MF, MachineOperand::CreateMBB(MBB, TargetFlags)); 105 MI->addOperand(*MF, MachineOperand::CreateFI(Idx)); in addFrameIndex() 112 MI->addOperand(*MF, MachineOperand::CreateCPI(Idx, Offset, TargetFlags)); 118 MI->addOperand(*MF, MachineOperand::CreateTargetIndex(Idx, Offset, 125 MI->addOperand(*MF, MachineOperand::CreateJTI(Idx, TargetFlags)); 132 MI->addOperand(*MF, MachineOperand::CreateGA(GV, Offset, TargetFlags)); [all …]
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/external/llvm/lib/Target/Hexagon/Disassembler/ |
D | HexagonDisassembler.cpp | 171 MI.addOperand(MCOperand::createInst(Inst)); in getInstruction() 310 MI.addOperand(OPLow); in getSingleInstruction() 311 MI.addOperand(OPHigh); in getSingleInstruction() 476 Inst.addOperand(MCOperand::createReg(Table[RegNo])); in DecodeRegisterClass() 578 Inst.addOperand(MCOperand::createReg(Register)); in DecodeCtrRegsRegisterClass() 602 Inst.addOperand(MCOperand::createReg(Register)); in DecodeCtrRegs64RegisterClass() 620 Inst.addOperand(MCOperand::createReg(Register)); in DecodeModRegsRegisterClass() 878 MI.addOperand(MCOperand::createImm(Value)); in decodeSpecial() 903 MI.addOperand(MCOperand::createImm(Value)); in decodeSpecial() 928 MI.addOperand(MCOperand::createImm(Value)); in decodeSpecial() [all …]
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/external/llvm/lib/Target/Hexagon/AsmParser/ |
D | HexagonAsmParser.cpp | 354 Inst.addOperand(MCOperand::createReg(getReg())); in addRegOperands() 359 Inst.addOperand(MCOperand::createExpr(getImm())); in addImmOperands() 367 Inst.addOperand(MCOperand::createExpr(Expr)); in addSignedImmOperands() 372 Inst.addOperand(MCOperand::createExpr(Expr)); in addSignedImmOperands() 377 Inst.addOperand(MCOperand::createImm(Extended)); in addSignedImmOperands() 557 Inst.addOperand(MCOperand::createImm(CE->getValue() * 64)); in adds4_6ImmOperands() 563 Inst.addOperand(MCOperand::createImm(CE->getValue() * 64)); in adds3_6ImmOperands() 768 NewInst.addOperand(MCOperand::createExpr( in canonicalizeImmediates() 772 NewInst.addOperand(I); in canonicalizeImmediates() 844 MCB.addOperand(MCOperand::createImm(0)); in MatchAndEmitInstruction() [all …]
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/external/llvm/lib/Target/X86/AsmParser/ |
D | X86Operand.h | 379 Inst.addOperand(MCOperand::createImm(CE->getValue())); in addExpr() 381 Inst.addOperand(MCOperand::createExpr(Expr)); in addExpr() 386 Inst.addOperand(MCOperand::createReg(getReg())); in addRegOperands() 417 Inst.addOperand(MCOperand::createReg(RegNo)); in addGR32orGR64Operands() 430 Inst.addOperand(MCOperand::createReg(getMemBaseReg())); in addMemOperands() 431 Inst.addOperand(MCOperand::createImm(getMemScale())); in addMemOperands() 432 Inst.addOperand(MCOperand::createReg(getMemIndexReg())); in addMemOperands() 434 Inst.addOperand(MCOperand::createReg(getMemSegReg())); in addMemOperands() 441 Inst.addOperand(MCOperand::createImm(CE->getValue())); in addAbsMemOperands() 443 Inst.addOperand(MCOperand::createExpr(getMemDisp())); in addAbsMemOperands() [all …]
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/external/llvm/lib/Target/AArch64/Disassembler/ |
D | AArch64Disassembler.cpp | 272 Inst.addOperand(MCOperand::createReg(Register)); in DecodeFPR128RegisterClass() 301 Inst.addOperand(MCOperand::createReg(Register)); in DecodeFPR64RegisterClass() 322 Inst.addOperand(MCOperand::createReg(Register)); in DecodeFPR32RegisterClass() 343 Inst.addOperand(MCOperand::createReg(Register)); in DecodeFPR16RegisterClass() 364 Inst.addOperand(MCOperand::createReg(Register)); in DecodeFPR8RegisterClass() 385 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPR64RegisterClass() 397 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPR64spRegisterClass() 418 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPR32RegisterClass() 431 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPR32spRegisterClass() 452 Inst.addOperand(MCOperand::createReg(Register)); in DecodeVectorRegisterClass() [all …]
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/external/llvm/lib/Target/ARM/Disassembler/ |
D | ARMDisassembler.cpp | 877 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPRRegisterClass() 901 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); in DecodeGPRwithAPSRRegisterClass() 932 Inst.addOperand(MCOperand::createReg(RegisterPair)); in DecodeGPRPairRegisterClass() 962 Inst.addOperand(MCOperand::createReg(Register)); in DecodetcGPRRegisterClass() 997 Inst.addOperand(MCOperand::createReg(Register)); in DecodeSPRRegisterClass() 1023 Inst.addOperand(MCOperand::createReg(Register)); in DecodeDPRRegisterClass() 1057 Inst.addOperand(MCOperand::createReg(Register)); in DecodeQPRRegisterClass() 1076 Inst.addOperand(MCOperand::createReg(Register)); in DecodeDPairRegisterClass() 1099 Inst.addOperand(MCOperand::createReg(Register)); in DecodeDPairSpacedRegisterClass() 1109 Inst.addOperand(MCOperand::createImm(Val)); in DecodePredicateOperand() [all …]
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/external/llvm/lib/Target/AArch64/ |
D | AArch64AsmPrinter.cpp | 470 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg())); in EmitInstruction() 479 TmpInst.addOperand(Dest); in EmitInstruction() 503 Adrp.addOperand(MCOperand::createReg(AArch64::X0)); in EmitInstruction() 504 Adrp.addOperand(SymTLSDesc); in EmitInstruction() 509 Ldr.addOperand(MCOperand::createReg(AArch64::X1)); in EmitInstruction() 510 Ldr.addOperand(MCOperand::createReg(AArch64::X0)); in EmitInstruction() 511 Ldr.addOperand(SymTLSDescLo12); in EmitInstruction() 512 Ldr.addOperand(MCOperand::createImm(0)); in EmitInstruction() 517 Add.addOperand(MCOperand::createReg(AArch64::X0)); in EmitInstruction() 518 Add.addOperand(MCOperand::createReg(AArch64::X0)); in EmitInstruction() [all …]
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/external/llvm/lib/Target/Sparc/Disassembler/ |
D | SparcDisassembler.cpp | 140 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeIntRegsRegisterClass() 151 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeI64RegsRegisterClass() 163 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPRegsRegisterClass() 175 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeDFPRegsRegisterClass() 190 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeQFPRegsRegisterClass() 199 Inst.addOperand(MCOperand::createReg(FCCRegDecoderTable[RegNo])); in DecodeFCCRegsRegisterClass() 208 Inst.addOperand(MCOperand::createReg(ASRRegDecoderTable[RegNo])); in DecodeASRRegsRegisterClass() 217 Inst.addOperand(MCOperand::createReg(PRRegDecoderTable[RegNo])); in DecodePRRegsRegisterClass() 232 Inst.addOperand(MCOperand::createReg(RegisterPair)); in DecodeIntPairRegisterClass() 345 MI.addOperand(MCOperand::createImm(simm13)); in DecodeMem() [all …]
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/external/llvm/lib/Target/AMDGPU/ |
D | SILowerI1Copies.cpp | 124 .addOperand(Dst) in runOnMachineFunction() 132 .addOperand(Dst) in runOnMachineFunction() 135 .addOperand(Src); in runOnMachineFunction() 140 .addOperand(Dst) in runOnMachineFunction() 141 .addOperand(Src) in runOnMachineFunction()
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/external/llvm/lib/Target/X86/ |
D | X86FixupLEAs.cpp | 117 .addOperand(Dest) in postRAConvertToLEA() 118 .addOperand(Src) in postRAConvertToLEA() 281 .addOperand(MI->getOperand(0)) in fixupIncDec() 282 .addOperand(MI->getOperand(1)); in fixupIncDec() 372 .addOperand(Dst) in processInstructionForSLM() 373 .addOperand(Src1) in processInstructionForSLM() 374 .addOperand(Src2); in processInstructionForSLM() 382 .addOperand(Dst) in processInstructionForSLM() 383 .addOperand(SrcR) in processInstructionForSLM()
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D | X86MCInstLower.cpp | 316 Inst.addOperand(Saved); in SimplifyShortImmForm() 395 Inst.addOperand(Saved); in SimplifyShortMoveForm() 396 Inst.addOperand(Seg); in SimplifyShortMoveForm() 441 OutMI.addOperand(MaybeMCOp.getValue()); in Lower() 525 OutMI.addOperand(Saved); in Lower() 549 OutMI.addOperand(MCOperand::createReg(ReturnReg)); in Lower() 568 OutMI.addOperand(Saved); in Lower() 748 LEA.addOperand(MCOperand::createReg(X86::RDI)); // dest in LowerTlsAddr() 749 LEA.addOperand(MCOperand::createReg(X86::RIP)); // base in LowerTlsAddr() 750 LEA.addOperand(MCOperand::createImm(1)); // scale in LowerTlsAddr() [all …]
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/external/llvm/lib/Target/SystemZ/ |
D | SystemZLongBranch.cpp | 352 .addOperand(MI->getOperand(0)) in splitBranchOnCount() 353 .addOperand(MI->getOperand(1)) in splitBranchOnCount() 358 .addOperand(MI->getOperand(2)); in splitBranchOnCount() 371 .addOperand(MI->getOperand(0)) in splitCompareBranch() 372 .addOperand(MI->getOperand(1)); in splitCompareBranch() 375 .addOperand(MI->getOperand(2)) in splitCompareBranch() 376 .addOperand(MI->getOperand(3)); in splitCompareBranch()
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