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Searched refs:add_a (Results 1 – 9 of 9) sorted by relevance

/external/chromium-trace/catapult/third_party/gsutil/third_party/boto/tests/integration/route53/
Dtest_zone.py48 self.zone.add_a(self.base_domain, '102.11.23.1', 80)
122 self.zone.add_a('wrr.%s' % self.base_domain, '1.2.3.4',
124 self.zone.add_a('wrr.%s' % self.base_domain, '5.6.7.8',
135 self.zone.add_a('lbr.%s' % self.base_domain, '4.3.2.1',
137 self.zone.add_a('lbr.%s' % self.base_domain, '8.7.6.5',
151 self.zone.add_a('exception.%s' % self.base_domain, '4.3.2.1',
153 self.zone.add_a('exception.%s' % self.base_domain, '8.7.6.5',
Dtest_alias_resourcerecordsets.py40 self.zone.add_a('target.%s' % self.base_domain, '102.11.23.1')
/external/llvm/test/MC/Mips/
Dmips-reginfo-fp64.s59 add_a.b $w26,$w26,$w26
60 add_a.b $w27,$w27,$w27
/external/llvm/test/MC/Mips/msa/
Dtest_3r.s3 # CHECK: add_a.b $w26, $w9, $w4 # encoding: [0x78,0x04,0x4e,0x90]
4 # CHECK: add_a.h $w23, $w27, $w31 # encoding: [0x78,0x3f,0xdd,0xd0]
5 # CHECK: add_a.w $w11, $w6, $w22 # encoding: [0x78,0x56,0x32,0xd0]
6 # CHECK: add_a.d $w6, $w10, $w0 # encoding: [0x78,0x60,0x51,0x90]
246 add_a.b $w26, $w9, $w4
247 add_a.h $w23, $w27, $w31
248 add_a.w $w11, $w6, $w22
249 add_a.d $w6, $w10, $w0
/external/llvm/test/MC/Disassembler/Mips/msa/
Dtest_3r.txt3 0x78 0x04 0x4e 0x90 # CHECK: add_a.b $w26, $w9, $w4
4 0x78 0x3f 0xdd 0xd0 # CHECK: add_a.h $w23, $w27, $w31
5 0x78 0x56 0x32 0xd0 # CHECK: add_a.w $w11, $w6, $w22
6 0x78 0x60 0x51 0x90 # CHECK: add_a.d $w6, $w10, $w0
/external/llvm/test/Transforms/LoopVectorize/AArch64/
Dloop-vectorization-factors.ll6 ; CHECK-LABEL: @add_a(
11 define void @add_a(i8* noalias nocapture readonly %p, i8* noalias nocapture %q, i32 %len) #0 {
/external/chromium-trace/catapult/third_party/gsutil/third_party/boto/boto/route53/
Dzone.py173 def add_a(self, name, value, ttl=None, identifier=None, comment=""): member in Zone
/external/llvm/test/CodeGen/Mips/msa/
D3r-a.ll32 ; CHECK-DAG: add_a.b [[WD:\$w[0-9]+]], [[WS]], [[WT]]
57 ; CHECK-DAG: add_a.h [[WD:\$w[0-9]+]], [[WS]], [[WT]]
82 ; CHECK-DAG: add_a.w [[WD:\$w[0-9]+]], [[WS]], [[WT]]
107 ; CHECK-DAG: add_a.d [[WD:\$w[0-9]+]], [[WS]], [[WT]]
/external/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td1511 class ADD_A_B_DESC : MSA_3R_DESC_BASE<"add_a.b", int_mips_add_a_b, MSA128BOpnd>,
1513 class ADD_A_H_DESC : MSA_3R_DESC_BASE<"add_a.h", int_mips_add_a_h, MSA128HOpnd>,
1515 class ADD_A_W_DESC : MSA_3R_DESC_BASE<"add_a.w", int_mips_add_a_w, MSA128WOpnd>,
1517 class ADD_A_D_DESC : MSA_3R_DESC_BASE<"add_a.d", int_mips_add_a_d, MSA128DOpnd>,