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Searched refs:ds_write2_b32 (Results 1 – 9 of 9) sorted by relevance

/external/llvm/test/MC/AMDGPU/
Dds-err.s10 ds_write2_b32 v2, v4, v6 offset0:4 offset0:8 label
14 ds_write2_b32 v2, v4, v6 offset1:4 offset1:8 label
18 ds_write2_b32 v2, v4, v6 offset0:1000000000 label
22 ds_write2_b32 v2, v4, v6 offset1:1000000000 label
Dds.s15 ds_write2_b32 v2, v4, v6 offset0:4 label
18 ds_write2_b32 v2, v4, v6 offset0:4 offset1:8 label
21 ds_write2_b32 v2, v4, v6 offset1:8 label
78 ds_write2_b32 v2, v4, v6 label
/external/llvm/test/CodeGen/AMDGPU/
Dds_write2.ll10 ; SI: ds_write2_b32 [[VPTR]], [[VAL]], [[VAL]] offset1:8
28 ; SI: ds_write2_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset1:8
45 ; SI-NOT: ds_write2_b32
64 ; SI-NOT: ds_write2_b32
87 ; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset1:8
108 ; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset1:8
127 ; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset1:8
147 ; SI: ds_write2_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset1:255
182 ; SI: ds_write2_b32 [[BASEADDR:v[0-9]+]], [[VAL0:v[0-9]+]], [[VAL1:v[0-9]+]] offset1:8
183 ; SI-NEXT: ds_write2_b32 [[BASEADDR]], [[VAL0]], [[VAL1]] offset0:11 offset1:27
[all …]
Dllvm.memcpy.ll140 ; SI: ds_write2_b32
141 ; SI: ds_write2_b32
142 ; SI: ds_write2_b32
143 ; SI: ds_write2_b32
Dunaligned-load-store.ll228 ; SI: ds_write2_b32
236 ; SI: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:8 offset1:9
246 ; SI: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset1:1
Dds-sub-offset.ll98 ; GCN: ds_write2_b32 [[NEG]], {{v[0-9]+}}, {{v[0-9]+}} offset0:254 offset1:255
112 ; GCN: ds_write2_b32 [[NEG]], {{v[0-9]+}}, {{v[0-9]+}} offset1:1{{$}}
Dstore.ll309 ; SI: ds_write2_b32
310 ; SI: ds_write2_b32
Dmerge-stores.ll525 ; GCN: ds_write2_b32 v{{[0-9]+}}, v[[LO]], v[[HI]] offset1:1{{$}}
537 ; GCN-DAG: ds_write2_b32 v{{[0-9]+}}, [[K2]], [[K3]] offset0:2 offset1:3
541 ; GCN-DAG: ds_write2_b32 v{{[0-9]+}}, [[K0]], [[K1]] offset1:1
/external/llvm/lib/Target/AMDGPU/
DSIInstructions.td777 defm DS_WRITE2_B32 : DS_1A1D_Off8_NORET <0xe, "ds_write2_b32", VGPR_32>;