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Searched refs:dst_chan (Results 1 – 3 of 3) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_wm_emit.c774 int dst_chan = ffs(mask & WRITEMASK_XYZW) - 1; in emit_dp2() local
784 brw_MAC(p, dst[dst_chan], arg0[1], arg1[1]); in emit_dp2()
795 int dst_chan = ffs(mask & WRITEMASK_XYZW) - 1; in emit_dp3() local
806 brw_MAC(p, dst[dst_chan], arg0[2], arg1[2]); in emit_dp3()
817 int dst_chan = ffs(mask & WRITEMASK_XYZW) - 1; in emit_dp4() local
829 brw_MAC(p, dst[dst_chan], arg0[3], arg1[3]); in emit_dp4()
840 const int dst_chan = ffs(mask & WRITEMASK_XYZW) - 1; in emit_dph() local
849 brw_MAC(p, dst[dst_chan], arg0[2], arg1[2]); in emit_dph()
852 brw_ADD(p, dst[dst_chan], dst[dst_chan], arg1[3]); in emit_dph()
890 int dst_chan = ffs(mask & WRITEMASK_XYZW) - 1; in emit_math1() local
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Dbrw_wm_fp.c257 unsigned int dst_chan; in emit_scalar_insn() local
263 dst_chan = ffs(inst0->DstReg.WriteMask) - 1; in emit_scalar_insn()
266 inst->DstReg.WriteMask = 1 << dst_chan; in emit_scalar_insn()
268 other_channel_mask = inst0->DstReg.WriteMask & ~(1 << dst_chan); in emit_scalar_insn()
274 src_swizzle1(src_reg_from_dst(inst0->DstReg), dst_chan), in emit_scalar_insn()
/external/llvm/lib/Target/AMDGPU/
DR600InstrFormats.td112 bits<2> dst_chan = dst{10-9};
117 let Word1{30-29} = dst_chan;
167 bits<2> dst_chan = 0;
175 let Word1{30-29} = dst_chan;