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Searched refs:hw (Results 1 – 25 of 172) sorted by relevance

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/external/mesa3d/src/mesa/drivers/dri/r200/
Dr200_cmdbuf.c61 make_empty_list(&rmesa->radeon.hw.atomlist); in r200SetUpAtomList()
62 rmesa->radeon.hw.atomlist.name = "atom-list"; in r200SetUpAtomList()
64 insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.ctx ); in r200SetUpAtomList()
65 insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.set ); in r200SetUpAtomList()
66 insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.lin ); in r200SetUpAtomList()
67 insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.msk ); in r200SetUpAtomList()
68 insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.vpt ); in r200SetUpAtomList()
69 insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.vtx ); in r200SetUpAtomList()
70 insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.vap ); in r200SetUpAtomList()
71 insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.vte ); in r200SetUpAtomList()
[all …]
Dr200_state_init.c338 if (r200->hw.set.cmd[SET_RE_CNTL] & R200_STIPPLE_ENABLE) in check_polygon_stipple()
625 rmesa->radeon.hw.max_state_size = 0; in r200InitState()
629 rmesa->hw.ATOM.cmd_size = SZ; \ in r200InitState()
630 rmesa->hw.ATOM.cmd = (GLuint *)CALLOC(SZ * sizeof(int)); \ in r200InitState()
631 rmesa->hw.ATOM.lastcmd = (GLuint *)CALLOC(SZ * sizeof(int)); \ in r200InitState()
632 rmesa->hw.ATOM.name = NM; \ in r200InitState()
633 rmesa->hw.ATOM.idx = IDX; \ in r200InitState()
635 rmesa->hw.ATOM.check = check_##CHK; \ in r200InitState()
636 rmesa->radeon.hw.max_state_size += SZ * sizeof(int); \ in r200InitState()
638 rmesa->hw.ATOM.check = NULL; \ in r200InitState()
[all …]
Dr200_state.c70 int pp_misc = rmesa->hw.ctx.cmd[CTX_PP_MISC]; in r200AlphaFunc()
107 rmesa->hw.ctx.cmd[CTX_PP_MISC] = pp_misc; in r200AlphaFunc()
119 …rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCOLOR] = radeonPackColor( 4, color[0], color[1], color[2], color[3… in r200BlendColor()
205 GLuint cntl = rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] & in r200_set_blend_state()
218 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = cntl | R200_ROP_ENABLE; in r200_set_blend_state()
219 rmesa->hw.ctx.cmd[CTX_RB3D_ABLENDCNTL] = eqn | func; in r200_set_blend_state()
220 rmesa->hw.ctx.cmd[CTX_RB3D_CBLENDCNTL] = eqn | func; in r200_set_blend_state()
223 … rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = cntl | R200_ALPHA_BLEND_ENABLE | R200_SEPARATE_ALPHA_ENABLE; in r200_set_blend_state()
226 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = cntl; in r200_set_blend_state()
227 rmesa->hw.ctx.cmd[CTX_RB3D_ABLENDCNTL] = eqn | func; in r200_set_blend_state()
[all …]
Dr200_fragshader.c135 afs_cmd = (GLuint *) rmesa->hw.afs[1].cmd; in r200UpdateFSArith()
138 afs_cmd = (GLuint *) rmesa->hw.afs[0].cmd; in r200UpdateFSArith()
320 afs_cmd = (GLuint *) rmesa->hw.afs[1].cmd; in r200UpdateFSArith()
341 rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~(R200_MULTI_PASS_ENABLE | in r200UpdateFSRouting()
344 rmesa->hw.cst.cmd[CST_PP_CNTL_X] &= ~(R200_PPX_PFS_INST_ENABLE_MASK | in r200UpdateFSRouting()
351 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= shader->numArithInstr[0] == 8 ? in r200UpdateFSRouting()
355 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_MULTI_PASS_ENABLE; in r200UpdateFSRouting()
356 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= shader->numArithInstr[1] == 8 ? in r200UpdateFSRouting()
359 rmesa->hw.cst.cmd[CST_PP_CNTL_X] |= in r200UpdateFSRouting()
367 rmesa->hw.tex[reg].cmd[TEX_PP_TXMULTI_CTL] = 0; in r200UpdateFSRouting()
[all …]
Dr200_ioctl.h88 rmesa->hw.ATOM.dirty = GL_TRUE; \
89 rmesa->radeon.hw.is_dirty = GL_TRUE; \
96 if (__dword != (rmesa)->hw.ATOM.cmd[__index]) { \
98 (rmesa)->hw.ATOM.cmd[__index] = __dword; \
103 memcpy( rmesa->hw.ATOM.lastcmd, rmesa->hw.ATOM.cmd, \
104 rmesa->hw.ATOM.cmd_size * 4)
114 rmesa->radeon.hw.is_dirty = GL_TRUE; in R200_DB_STATECHANGE()
Dr200_tcl.c131 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] |= \
134 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] &= \
273 if (rmesa->hw.set.cmd[SET_RE_CNTL] & R200_PERSPECTIVE_ENABLE) { in r200TclPrimitive()
275 rmesa->hw.set.cmd[SET_RE_CNTL] &= ~R200_PERSPECTIVE_ENABLE; in r200TclPrimitive()
278 else if (!(rmesa->hw.set.cmd[SET_RE_CNTL] & R200_PERSPECTIVE_ENABLE)) { in r200TclPrimitive()
280 rmesa->hw.set.cmd[SET_RE_CNTL] |= R200_PERSPECTIVE_ENABLE; in r200TclPrimitive()
314 if (!rmesa->hw.vtx.dirty) in r200EnsureEmitSize()
315 state_size += rmesa->hw.vtx.check(rmesa->radeon.glCtx, &rmesa->hw.vtx); in r200EnsureEmitSize()
453 if (rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] != out_compsel) { in r200_run_tcl_render()
455 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] = out_compsel; in r200_run_tcl_render()
[all …]
Dr200_swtcl.c177 if ( (rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] & R200_FOG_USE_MASK) in r200SetVertexFormat()
180 rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] &= ~R200_FOG_USE_MASK; in r200SetVertexFormat()
181 rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] |= R200_FOG_USE_SPEC_ALPHA; in r200SetVertexFormat()
185 (rmesa->hw.vtx.cmd[VTX_VTXFMT_0] != fmt_0) || in r200SetVertexFormat()
186 (rmesa->hw.vtx.cmd[VTX_VTXFMT_1] != fmt_1) ) { in r200SetVertexFormat()
189 rmesa->hw.vtx.cmd[VTX_VTXFMT_0] = fmt_0; in r200SetVertexFormat()
190 rmesa->hw.vtx.cmd[VTX_VTXFMT_1] = fmt_1; in r200SetVertexFormat()
250 vte = rmesa->hw.vte.cmd[VTE_SE_VTE_CNTL]; in r200ChooseVertexState()
251 vap = rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL]; in r200ChooseVertexState()
277 if (vte != rmesa->hw.vte.cmd[VTE_SE_VTE_CNTL]) { in r200ChooseVertexState()
[all …]
Dr200_texstate.c308 GLuint color_scale = rmesa->hw.pix[slot].cmd[PIX_PP_TXCBLEND2] & in r200UpdateTextureEnv()
311 GLuint alpha_scale = rmesa->hw.pix[slot].cmd[PIX_PP_TXABLEND2] & in r200UpdateTextureEnv()
714 if ( rmesa->hw.pix[slot].cmd[PIX_PP_TXCBLEND] != color_combine || in r200UpdateTextureEnv()
715 rmesa->hw.pix[slot].cmd[PIX_PP_TXABLEND] != alpha_combine || in r200UpdateTextureEnv()
716 rmesa->hw.pix[slot].cmd[PIX_PP_TXCBLEND2] != color_scale || in r200UpdateTextureEnv()
717 rmesa->hw.pix[slot].cmd[PIX_PP_TXABLEND2] != alpha_scale) { in r200UpdateTextureEnv()
719 rmesa->hw.pix[slot].cmd[PIX_PP_TXCBLEND] = color_combine; in r200UpdateTextureEnv()
720 rmesa->hw.pix[slot].cmd[PIX_PP_TXABLEND] = alpha_combine; in r200UpdateTextureEnv()
721 rmesa->hw.pix[slot].cmd[PIX_PP_TXCBLEND2] = color_scale; in r200UpdateTextureEnv()
722 rmesa->hw.pix[slot].cmd[PIX_PP_TXABLEND2] = alpha_scale; in r200UpdateTextureEnv()
[all …]
/external/mesa3d/src/mesa/drivers/dri/radeon/
Dradeon_state.c69 int pp_misc = rmesa->hw.ctx.cmd[CTX_PP_MISC]; in radeonAlphaFunc()
106 rmesa->hw.ctx.cmd[CTX_PP_MISC] = pp_misc; in radeonAlphaFunc()
113 GLuint b = rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] & ~RADEON_COMB_FCN_MASK; in radeonBlendEquationSeparate()
139 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = b; in radeonBlendEquationSeparate()
142 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_ROP_ENABLE; in radeonBlendEquationSeparate()
144 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~RADEON_ROP_ENABLE; in radeonBlendEquationSeparate()
154 GLuint b = rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] & in radeonBlendFuncSeparate()
252 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = b; in radeonBlendFuncSeparate()
266 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_Z_TEST_MASK; in radeonDepthFunc()
270 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_TEST_NEVER; in radeonDepthFunc()
[all …]
Dradeon_state_init.c512 rmesa->radeon.hw.max_state_size = 0; in radeonInitState()
516 rmesa->hw.ATOM.cmd_size = SZ; \ in radeonInitState()
517 rmesa->hw.ATOM.cmd = (GLuint *)CALLOC(SZ * sizeof(int)); \ in radeonInitState()
518 rmesa->hw.ATOM.lastcmd = (GLuint *)CALLOC(SZ * sizeof(int)); \ in radeonInitState()
519 rmesa->hw.ATOM.name = NM; \ in radeonInitState()
520 rmesa->hw.ATOM.is_tcl = FLAG; \ in radeonInitState()
521 rmesa->hw.ATOM.check = check_##CHK; \ in radeonInitState()
522 rmesa->hw.ATOM.dirty = GL_TRUE; \ in radeonInitState()
523 rmesa->hw.ATOM.idx = IDX; \ in radeonInitState()
524 rmesa->radeon.hw.max_state_size += SZ * sizeof(int); \ in radeonInitState()
[all …]
Dradeon_ioctl.c69 make_empty_list(&rmesa->radeon.hw.atomlist); in radeonSetUpAtomList()
70 rmesa->radeon.hw.atomlist.name = "atom-list"; in radeonSetUpAtomList()
72 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.ctx); in radeonSetUpAtomList()
73 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.set); in radeonSetUpAtomList()
74 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.lin); in radeonSetUpAtomList()
75 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.msk); in radeonSetUpAtomList()
76 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.vpt); in radeonSetUpAtomList()
77 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.tcl); in radeonSetUpAtomList()
78 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.msc); in radeonSetUpAtomList()
80 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.tex[i]); in radeonSetUpAtomList()
[all …]
Dradeon_tcl.c135 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] |= \
138 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] &= \
265 se_cntl = rmesa->hw.set.cmd[SET_SE_CNTL]; in radeonTclPrimitive()
273 if (se_cntl != rmesa->hw.set.cmd[SET_SE_CNTL]) { in radeonTclPrimitive()
275 rmesa->hw.set.cmd[SET_SE_CNTL] = se_cntl; in radeonTclPrimitive()
316 if (!rmesa->hw.tcl.dirty) in radeonEnsureEmitSize()
317 state_size += rmesa->hw.tcl.check( rmesa->radeon.glCtx, &rmesa->hw.tcl ); in radeonEnsureEmitSize()
471 se_cntl = rmesa->hw.set.cmd[SET_SE_CNTL]; in transition_to_swtnl()
474 if (se_cntl != rmesa->hw.set.cmd[SET_SE_CNTL]) { in transition_to_swtnl()
476 rmesa->hw.set.cmd[SET_SE_CNTL] = se_cntl; in transition_to_swtnl()
[all …]
Dradeon_ioctl.h105 rmesa->hw.ATOM.dirty = GL_TRUE; \
106 rmesa->radeon.hw.is_dirty = GL_TRUE; \
110 memcpy( rmesa->hw.ATOM.lastcmd, rmesa->hw.ATOM.cmd, \
111 rmesa->hw.ATOM.cmd_size * 4)
120 rmesa->radeon.hw.is_dirty = GL_TRUE; in RADEON_DB_STATECHANGE()
/external/avahi/avahi-core/
Diface.c113 void avahi_hw_interface_update_rrs(AvahiHwInterface *hw, int remove_rrs) { in avahi_hw_interface_update_rrs() argument
117 assert(hw); in avahi_hw_interface_update_rrs()
118 m = hw->monitor; in avahi_hw_interface_update_rrs()
120 for (i = hw->interfaces; i; i = i->by_hardware_next) in avahi_hw_interface_update_rrs()
128 if (!hw->entry_group) in avahi_hw_interface_update_rrs()
129 … hw->entry_group = avahi_s_entry_group_new(m->server, avahi_host_rr_entry_group_callback, NULL); in avahi_hw_interface_update_rrs()
131 if (!hw->entry_group) in avahi_hw_interface_update_rrs()
134 if (avahi_s_entry_group_is_empty(hw->entry_group)) { in avahi_hw_interface_update_rrs()
139 avahi_format_mac_address(mac, sizeof(mac), hw->mac_address, hw->mac_address_size); in avahi_hw_interface_update_rrs()
142 …if (avahi_server_add_service(m->server, hw->entry_group, hw->index, AVAHI_PROTO_UNSPEC, 0, name, "… in avahi_hw_interface_update_rrs()
[all …]
Diface-linux.c80 AvahiHwInterface *hw; in netlink_callback() local
93 if (!(hw = avahi_interface_monitor_get_hw_interface(m, ifinfomsg->ifi_index))) in netlink_callback()
100 if (!(hw = avahi_hw_interface_new(m, (AvahiIfIndex) ifinfomsg->ifi_index))) in netlink_callback()
104 hw->flags_ok = in netlink_callback()
120 avahi_free(hw->name); in netlink_callback()
121 hw->name = avahi_strndup(RTA_DATA(a), RTA_PAYLOAD(a)); in netlink_callback()
128 hw->mtu = *((unsigned int*) RTA_DATA(a)); in netlink_callback()
134 hw->mac_address_size = RTA_PAYLOAD(a); in netlink_callback()
135 if (hw->mac_address_size > AVAHI_MAC_ADDRESS_MAX) in netlink_callback()
136 hw->mac_address_size = AVAHI_MAC_ADDRESS_MAX; in netlink_callback()
[all …]
Diface-pfroute.c62 AvahiHwInterface *hw; in rtm_info() local
70 if (!(hw = avahi_interface_monitor_get_hw_interface(m, (AvahiIfIndex) ifm->ifm_index))) in rtm_info()
72 avahi_hw_interface_free(hw, 0); in rtm_info()
76 if (!(hw = avahi_interface_monitor_get_hw_interface(m, ifm->ifm_index))) in rtm_info()
77 if (!(hw = avahi_hw_interface_new(m, (AvahiIfIndex) ifm->ifm_index))) in rtm_info()
80 hw->flags_ok = in rtm_info()
87 avahi_free(hw->name); in rtm_info()
88 hw->name = avahi_strndup(sdl->sdl_data, sdl->sdl_nlen); in rtm_info()
90 hw->mtu = ifm->ifm_data.ifi_mtu; in rtm_info()
92 hw->mac_address_size = sdl->sdl_alen; in rtm_info()
[all …]
/external/mesa3d/src/mesa/drivers/dri/nouveau/
Dnv04_context.c52 struct nouveau_hw_state *hw = &to_nouveau_context(ctx)->hw; in nv04_context_engine() local
64 fahrenheit = hw->eng3dm; in nv04_context_engine()
66 fahrenheit = hw->eng3d; in nv04_context_engine()
80 struct nouveau_hw_state *hw = &to_nouveau_context(ctx)->hw; in nv04_hwctx_init() local
82 struct nv04_fifo *fifo = hw->chan->data; in nv04_hwctx_init()
85 PUSH_DATA (push, hw->surf3d->handle); in nv04_hwctx_init()
87 PUSH_DATA (push, hw->ntfy->handle); in nv04_hwctx_init()
92 PUSH_DATA (push, hw->eng3d->handle); in nv04_hwctx_init()
94 PUSH_DATA (push, hw->ntfy->handle); in nv04_hwctx_init()
97 PUSH_DATA (push, hw->surf3d->handle); in nv04_hwctx_init()
[all …]
Dnv04_surface.c204 struct nouveau_hw_state *hw = &to_nouveau_context(ctx)->hw; in nv04_surface_copy_swizzle() local
205 struct nouveau_object *swzsurf = hw->swzsurf; in nv04_surface_copy_swizzle()
206 struct nv04_fifo *fifo = hw->chan->data; in nv04_surface_copy_swizzle()
269 PUSH_DATA (push, hw->surf3d->handle); in nv04_surface_copy_swizzle()
285 struct nouveau_hw_state *hw = &to_nouveau_context(ctx)->hw; in nv04_surface_copy_m2mf() local
286 struct nv04_fifo *fifo = hw->chan->data; in nv04_surface_copy_m2mf()
433 struct nouveau_hw_state *hw = &to_nouveau_context(ctx)->hw; in nv04_surface_fill() local
434 struct nv04_fifo *fifo = hw->chan->data; in nv04_surface_fill()
466 struct nouveau_hw_state *hw = &to_nouveau_context(ctx)->hw; in nv04_surface_takedown() local
468 nouveau_object_del(&hw->swzsurf); in nv04_surface_takedown()
[all …]
Dnouveau_context.c154 }, sizeof(struct nv04_fifo), &nctx->hw.chan); in nouveau_context_init()
161 ret = nouveau_client_new(context_dev(ctx), &nctx->hw.client); in nouveau_context_init()
168 ret = nouveau_pushbuf_new(nctx->hw.client, nctx->hw.chan, 4, in nouveau_context_init()
169 512 * 1024, true, &nctx->hw.pushbuf); in nouveau_context_init()
176 ret = nouveau_bufctx_new(nctx->hw.client, 16, &nctx->hw.bufctx); in nouveau_context_init()
182 nctx->hw.pushbuf->user_priv = nctx->hw.bufctx; in nouveau_context_init()
185 ret = nouveau_object_new(nctx->hw.chan, 0x00000000, NV01_NULL_CLASS, in nouveau_context_init()
186 NULL, 0, &nctx->hw.null); in nouveau_context_init()
224 nouveau_bufctx_del(&nctx->hw.bufctx); in nouveau_context_deinit()
225 nouveau_pushbuf_del(&nctx->hw.pushbuf); in nouveau_context_deinit()
[all …]
/external/mesa3d/src/gallium/drivers/nv30/
Dnvfx_fragprog.c90 uint32_t *hw = &fp->insn[fpc->inst_offset]; in emit_src() local
96 hw[0] |= (src.reg.index << NVFX_FP_OP_INPUT_SRC_SHIFT); in emit_src()
108 hw = &fp->insn[fpc->inst_offset]; in emit_src()
121 hw = &fp->insn[fpc->inst_offset]; in emit_src()
149 hw[1] |= (1 << (29 + pos)); in emit_src()
156 hw[pos + 1] |= sr; in emit_src()
163 uint32_t *hw = &fp->insn[fpc->inst_offset]; in emit_dst() local
170 hw[0] |= NVFX_FP_OP_OUT_REG_HALF; in emit_dst()
179 hw[0] |= (1 << 30); in emit_dst()
185 hw[0] |= (dst.index << NVFX_FP_OP_OUT_REG_SHIFT); in emit_dst()
[all …]
Dnvfx_vertprog.c117 emit_src(struct nv30_context *nv30, struct nvfx_vpc *vpc, uint32_t *hw, in emit_src() argument
133 hw[1] |= (src.reg.index << NVFX_VP(INST_INPUT_SRC_SHIFT)); in emit_src()
143 hw[1] |= (src.reg.index << NVFX_VP(INST_CONST_SRC_SHIFT)) & in emit_src()
159 hw[0] |= (1 << (21 + pos)); in emit_src()
168 hw[3] |= NVFX_VP(INST_INDEX_CONST); in emit_src()
170 hw[0] |= NVFX_VP(INST_INDEX_INPUT); in emit_src()
175 hw[0] |= NVFX_VP(INST_ADDR_REG_SELECT_1); in emit_src()
176 hw[0] |= src.indirect_swz << NVFX_VP(INST_ADDR_SWZ_SHIFT); in emit_src()
181 hw[1] |= ((sr & NVFX_VP(SRC0_HIGH_MASK)) >> in emit_src()
183 hw[2] |= (sr & NVFX_VP(SRC0_LOW_MASK)) << in emit_src()
[all …]
Dnv30_query.c36 struct nouveau_heap *hw; member
46 if (qo && qo->hw) in nv30_ntfy()
47 ntfy = (char *)notify->map + query->offset + qo->hw->start; in nv30_ntfy()
60 nouveau_heap_free(&qo->hw); in nv30_query_object_del()
78 while (nouveau_heap_alloc(screen->query_heap, 32, NULL, &qo->hw)) { in nv30_query_object_new()
159 PUSH_DATA (push, (q->report << 24) | q->qo[0]->hw->start); in nv30_query_begin()
187 PUSH_DATA (push, (q->report << 24) | q->qo[1]->hw->start); in nv30_query_end()
254 PUSH_DATA (push, 0x02000000 | q->qo[1]->hw->start); in nv40_query_render_condition()
/external/regex-re2/benchlog/
Dbenchlog.mini1 hw.ncpu: 2
2 hw.byteorder: 1234
3 hw.memsize: 4294967296
4 hw.activecpu: 2
5 hw.physicalcpu: 2
6 hw.physicalcpu_max: 2
7 hw.logicalcpu: 2
8 hw.logicalcpu_max: 2
9 hw.cputype: 7
10 hw.cpusubtype: 4
[all …]
/external/mesa3d/src/gallium/drivers/svga/
Dsvga_state_framebuffer.c46 struct pipe_framebuffer_state *hw = &svga->state.hw_clear.framebuffer; in emit_framebuffer() local
57 if (curr->cbufs[i] != hw->cbufs[i] || in emit_framebuffer()
58 (reemit && hw->cbufs[i])) { in emit_framebuffer()
66 pipe_surface_reference(&hw->cbufs[i], curr->cbufs[i]); in emit_framebuffer()
71 if (curr->zsbuf != hw->zsbuf || in emit_framebuffer()
72 (reemit && hw->zsbuf)) { in emit_framebuffer()
89 pipe_surface_reference(&hw->zsbuf, curr->zsbuf); in emit_framebuffer()
109 struct pipe_framebuffer_state *hw = &svga->state.hw_clear.framebuffer; in svga_reemit_framebuffer_bindings() local
116 if (hw->cbufs[i]) { in svga_reemit_framebuffer_bindings()
117 ret = SVGA3D_SetRenderTarget(svga->swc, SVGA3D_RT_COLOR0 + i, hw->cbufs[i]); in svga_reemit_framebuffer_bindings()
[all …]
/external/wpa_supplicant_8/src/ap/
Dhw_features.c516 u16 hw = iface->current_mode->ht_capab; in ieee80211n_supported_ht_capab() local
520 !(hw & HT_CAP_INFO_LDPC_CODING_CAP)) { in ieee80211n_supported_ht_capab()
531 !(hw & HT_CAP_INFO_SUPP_CHANNEL_WIDTH_SET)) { in ieee80211n_supported_ht_capab()
558 !(hw & HT_CAP_INFO_GREEN_FIELD)) { in ieee80211n_supported_ht_capab()
565 !(hw & HT_CAP_INFO_SHORT_GI20MHZ)) { in ieee80211n_supported_ht_capab()
572 !(hw & HT_CAP_INFO_SHORT_GI40MHZ)) { in ieee80211n_supported_ht_capab()
578 if ((conf & HT_CAP_INFO_TX_STBC) && !(hw & HT_CAP_INFO_TX_STBC)) { in ieee80211n_supported_ht_capab()
585 (hw & HT_CAP_INFO_RX_STBC_MASK)) { in ieee80211n_supported_ht_capab()
592 !(hw & HT_CAP_INFO_DELAYED_BA)) { in ieee80211n_supported_ht_capab()
599 !(hw & HT_CAP_INFO_MAX_AMSDU_SIZE)) { in ieee80211n_supported_ht_capab()
[all …]

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