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Searched refs:iPTR (Results 1 – 25 of 41) sorted by relevance

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/external/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrInfo.td28 def SDT_WebAssemblyCallSeqStart : SDCallSeqStart<[SDTCisVT<0, iPTR>]>;
30 SDCallSeqEnd<[SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
DWebAssemblyISelLowering.cpp244 assert(VT != MVT::iPTR && "Pointer MVT not expected here"); in getRegForInlineAsmConstraint()
375 assert(VT != MVT::iPTR && "Legalized args should be concrete"); in LowerCall()
/external/llvm/lib/Target/X86/
DX86InstrSSE.td333 def : Pat<(f32 (extractelt (v4f32 VR128:$src), (iPTR 0))),
335 def : Pat<(f64 (extractelt (v2f64 VR128:$src), (iPTR 0))),
340 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (iPTR 0))),
342 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (iPTR 0))),
345 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (iPTR 0))),
347 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (iPTR 0))),
350 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (iPTR 0))),
352 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (iPTR 0))),
358 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)),
360 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)),
[all …]
DX86InstrAVX512.td501 (iPTR imm))>, AVX512AIi8Base, EVEX_4V;
510 (iPTR imm))>, AVX512AIi8Base, EVEX_4V,
520 (To.VT To.RC:$src1), (From.VT From.RC:$src2), (iPTR imm)),
528 (iPTR imm)),
631 Pat<(To.VT (extract_subvector (From.VT From.RC:$src),(iPTR 0))),
649 (iPTR imm)))]>,
671 From.RC:$src1, (iPTR imm:$idx), To.RC:$src0, To.MRC:$mask),
681 From.RC:$src1, (iPTR imm:$idx), To.ImmAllZerosV, To.MRC:$mask),
690 From.RC:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
703 def : Pat<(vextract_extract:$ext (From.VT From.RC:$src1), (iPTR imm)),
[all …]
DX86InstrFragmentsSIMD.td645 (f32 (extractelt (loadv4f32 node:$ptr), (iPTR 0)))>;
647 (f64 (extractelt (loadv2f64 node:$ptr), (iPTR 0)))>;
745 (f32 (extractelt (memopv4f32 node:$ptr), (iPTR 0)))>;
747 (f64 (extractelt (memopv2f64 node:$ptr), (iPTR 0)))>;
/external/llvm/lib/Target/Sparc/
DSparcInstr64Bit.td176 [(set iPTR:$dst, ADDRri:$addr)]>;
519 [(set i32:$rd, (op32 iPTR:$addr, i32:$rs2))]>;
524 [(set i64:$rd, (op64 iPTR:$addr, i64:$rs2))]>;
544 (atomic_swap_64 iPTR:$addr, i64:$rs2))]>;
570 def : Pat<(add iPTR:$r, (SPlo tglobaladdr:$in)), (ADDXri $r, tglobaladdr:$in)>;
571 def : Pat<(add iPTR:$r, (SPlo tconstpool:$in)), (ADDXri $r, tconstpool:$in)>;
572 def : Pat<(add iPTR:$r, (SPlo tblockaddress:$in)),
DSparcInstrInfo.td82 def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", [], []>;
83 def ADDRri : ComplexPattern<iPTR, 2, "SelectADDRri", [frameindex], []>;
96 def MEMrr : Operand<iPTR> {
101 def MEMri : Operand<iPTR> {
107 def TLSSym : Operand<iPTR>;
203 def getPCX : Operand<iPTR> {
586 [(set iPTR:$dst, ADDRri:$addr)]>;
1318 (atomic_cmp_swap iPTR:$rs1, i32:$rs2, i32:$swap))]>;
1382 def : Pat<(add iPTR:$r, (SPlo tglobaladdr:$in)), (ADDri $r, tglobaladdr:$in)>;
1383 def : Pat<(add iPTR:$r, (SPlo tconstpool:$in)), (ADDri $r, tconstpool:$in)>;
[all …]
/external/llvm/lib/Target/PowerPC/
DPPCInstr64Bit.td39 def tocentry : Operand<iPTR> {
1080 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1082 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1084 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1086 def : Pat<(aligned4pre_store i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1089 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1091 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1093 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1095 def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
DPPCInstrInfo.td53 def tocentry32 : Operand<iPTR> {
589 def calltarget : Operand<iPTR> {
594 def abscalltarget : Operand<iPTR> {
613 def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> {
620 def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> {
628 def dispRI : Operand<iPTR> {
635 def dispRIX : Operand<iPTR> {
642 def dispSPE8 : Operand<iPTR> {
649 def dispSPE4 : Operand<iPTR> {
656 def dispSPE2 : Operand<iPTR> {
[all …]
DPPCInstrQPX.td980 def : Pat<(pre_store v4f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
982 def : Pat<(pre_store v4f32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
984 def : Pat<(pre_truncstv4f32 v4f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
/external/llvm/utils/TableGen/
DDAGISelMatcher.cpp370 if (T1 == MVT::iPTR) in TypesAreContradictory()
373 if (T2 == MVT::iPTR) in TypesAreContradictory()
DCodeGenTarget.cpp45 case MVT::iPTR: return "TLI.getPointerTy()"; in getName()
126 case MVT::iPTR: return "MVT::iPTR"; in getEnumName()
DCodeGenDAGPatterns.cpp56 assert((VT < MVT::LAST_VALUETYPE || VT == MVT::iPTR || in TypeSet()
168 case MVT::iPTR: in MergeInTypeInfo()
190 if ((InVT.TypeVec[0] == MVT::iPTR || InVT.TypeVec[0] == MVT::iPTRAny) && in MergeInTypeInfo()
196 if ((InVT.TypeVec[0] == MVT::iPTR || InVT.TypeVec[0] == MVT::iPTRAny) && in MergeInTypeInfo()
1002 return NodeToApply->UpdateNodeType(ResNo, MVT::iPTR, TP); in ApplyTypeConstraint()
1113 return UpdateNodeType(ResNo, MVT::iPTR, TP); in UpdateNodeTypeFromInst()
1197 return MVT::iPTR; in getKnownType()
1564 return EEVT::TypeSet(MVT::iPTR, TP); in getImplicitType()
1725 if (VT == MVT::iPTR || VT == MVT::iPTRAny) in ApplyTypeConstraints()
1792 MadeChange |= getChild(0)->UpdateNodeType(0, MVT::iPTR, TP); in ApplyTypeConstraints()
DCodeGenDAGPatterns.h69 assert(T < MVT::LAST_VALUETYPE || T == MVT::iPTR || T == MVT::iPTRAny); in isConcrete()
79 return getConcrete() == MVT::iPTR || getConcrete() == MVT::iPTRAny; in isDynamicallyResolved()
DDAGISelMatcherOpt.cpp434 CTM->getType() == MVT::iPTR || in FactorNodes()
DIntrinsicEmitter.cpp350 case MVT::iPTR: { in EncodeFixedType()
/external/llvm/lib/Target/BPF/
DBPFInstrInfo.td19 def SDT_BPFCallSeqStart : SDCallSeqStart<[SDTCisVT<0, iPTR>]>;
20 def SDT_BPFCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
21 def SDT_BPFCall : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h172 iPTR = 255, enumerator
428 case iPTR: in getSizeInBits()
DValueTypes.td116 def iPTR : ValueType<0 , 255>;
/external/llvm/lib/Target/Mips/
DMipsInstrInfo.td19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
481 def calltarget : Operand<iPTR> {
650 class mem_generic : Operand<iPTR> {
691 def mem_ea : Operand<iPTR> {
698 def PtrRC : Operand<iPTR> {
766 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
769 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
772 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>;
775 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
777 def addrimm10 : ComplexPattern<iPTR, 2, "selectIntAddrMSA", [frameindex]>;
[all …]
DMipsInstrFPU.td198 [(set DRC:$fd, (OpNode (add iPTR:$base, iPTR:$index)))], Itin,
207 [(OpNode DRC:$fs, (add iPTR:$base, iPTR:$index))], Itin,
DMicroMipsInstrInfo.td1 def addrimm12 : ComplexPattern<iPTR, 2, "selectIntAddrMM", [frameindex]>;
2 def addrimm4lsl2 : ComplexPattern<iPTR, 2, "selectIntAddrLSL2MM", [frameindex]>;
148 def calltarget_mm : Operand<iPTR> {
/external/mesa3d/src/gallium/drivers/radeon/
DSIInstrInfo.td99 def SMRDmemrr : Operand<iPTR> {
104 def SMRDmemri : Operand<iPTR> {
/external/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGISel.cpp2380 return VT == MVT::iPTR && N.getValueType() == TLI->getPointerTy(DL); in CheckType()
2408 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI->getPointerTy(DL); in CheckValueType()
2913 if (CaseVT == MVT::iPTR) in SelectCodeCommon()
3148 if (VT == MVT::iPTR) in SelectCodeCommon()
3333 NodeToMatch->getValueType(i) == MVT::iPTR || in SelectCodeCommon()
3334 Res.getValueType() == MVT::iPTR || in SelectCodeCommon()
/external/llvm/lib/IR/
DValueTypes.cpp292 case Type::PointerTyID: return MVT(MVT::iPTR); in getVT()

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