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Searched refs:isAssignedRegDep (Results 1 – 5 of 5) sorted by relevance

/external/llvm/lib/CodeGen/
DScheduleDAG.cpp350 if (I->isAssignedRegDep()) in dumpAll()
370 if (I->isAssignedRegDep()) in dumpAll()
607 if (I->isAssignedRegDep() && in WillCreateCycle()
/external/llvm/lib/CodeGen/SelectionDAG/
DScheduleDAGVLIW.cpp144 assert(!I->isAssignedRegDep() && in releaseSuccessors()
DScheduleDAGFast.cpp166 if (I->isAssignedRegDep()) { in ReleasePredecessors()
196 if (I->isAssignedRegDep()) { in ScheduleNodeBottomUp()
484 if (I->isAssignedRegDep()) { in DelayForLiveRegsBottomUp()
DScheduleDAGRRList.cpp530 if (I->isAssignedRegDep()) { in ReleasePredecessors()
743 if (I->isAssignedRegDep() && LiveRegDefs[I->getReg()] == SU) { in ScheduleNodeBottomUp()
812 if (I->isAssignedRegDep() && SU == LiveRegGens[I->getReg()]){ in UnscheduleNodeBottomUp()
852 if (Succ.isAssignedRegDep()) { in UnscheduleNodeBottomUp()
866 if (Succ2.isAssignedRegDep() && Succ2.getReg() == Reg && in UnscheduleNodeBottomUp()
1280 if (I->isAssignedRegDep() && LiveRegDefs[I->getReg()] != SU) in DelayForLiveRegsBottomUp()
2734 if (!PI->isAssignedRegDep()) in canClobberReachingPhysRegUse()
2894 assert(!Edge.isAssignedRegDep()); in PrescheduleNodesWithMultipleUses()
/external/llvm/include/llvm/CodeGen/
DScheduleDAG.h228 bool isAssignedRegDep() const { in isAssignedRegDep() function