/external/llvm/lib/Target/WebAssembly/ |
D | WebAssemblyInstrControl.td | 25 let isBarrier = 1 in { 29 } // isBarrier = 1 44 let isTerminator = 1, hasCtrlDep = 1, isBarrier = 1 in { 51 } // isTerminator = 1, hasCtrlDep = 1, isBarrier = 1 67 let isTerminator = 1, hasCtrlDep = 1, isBarrier = 1 in { 76 } // isTerminator = 1, hasCtrlDep = 1, isBarrier = 1
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D | WebAssemblyInstrInfo.cpp | 97 if (MI.isBarrier()) in AnalyzeBranch()
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D | WebAssemblyCFGStackify.cpp | 202 !MBB.back().isBarrier()) in SortBlocks() 369 if (!Bottom->back().isBarrier()) in PlaceLoopMarker()
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/external/llvm/include/llvm/MC/ |
D | MCInstrDesc.h | 219 bool isBarrier() const { return Flags & (1 << MCID::Barrier); } in isBarrier() function 244 return isBranch() & !isBarrier() & !isIndirectBranch(); in isConditionalBranch() 252 return isBranch() & isBarrier() & !isIndirectBranch(); in isUnconditionalBranch()
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/external/llvm/test/CodeGen/AArch64/ |
D | atomic-ops-not-barriers.ll | 21 ; with isBarrier. For now, look for something that looks like "somewhere".
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/external/llvm/lib/Target/X86/ |
D | X86InstrControl.td | 22 let isTerminator = 1, isReturn = 1, isBarrier = 1, 72 let isBarrier = 1, isBranch = 1, isTerminator = 1, SchedRW = [WriteJump] in { 134 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 243 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, 296 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
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/external/llvm/lib/Target/ARM/ |
D | ARMHazardRecognizer.cpp | 52 if (!LastMI->isBarrier() && in getHazardType()
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D | ARMInstrThumb.td | 433 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 444 let isReturn = 1, isTerminator = 1, isBarrier = 1 in { 506 let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 550 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { 584 let isBarrier = 1, isTerminator = 1 in 1300 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1, 1307 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1, 1481 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, 1488 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
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D | MLxExpansionPass.cpp | 345 if (MI->isBarrier()) { in ExpandFPMLxInstructions()
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/external/llvm/include/llvm/CodeGen/ |
D | MachineInstr.h | 417 bool isBarrier(QueryType Type = AnyInBundle) const { 449 return isBranch(Type) & !isBarrier(Type) & !isIndirectBranch(Type); 457 return isBranch(Type) & isBarrier(Type) & !isIndirectBranch(Type);
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D | ScheduleDAG.h | 189 bool isBarrier() const { in isBarrier() function 196 return (isNormalMemory() || isBarrier()); in isNormalMemoryOrBarrier()
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/external/llvm/lib/Target/XCore/ |
D | XCoreInstrInfo.td | 347 let isReturn = 1, isTerminator = 1, isBarrier = 1 in 638 let isReturn = 1, isTerminator = 1, mayLoad = 1, isBarrier = 1 in { 649 let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 677 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1, 958 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in 963 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in 968 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in 973 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in 1107 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1,
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/external/llvm/lib/Target/Mips/ |
D | MipsInstrInfo.td | 365 bit isBarrier = 1; 971 let isBarrier=1; 983 let isBarrier = 1; 990 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in 1028 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1, 1045 let isBarrier = 1; 1253 let isBarrier = 1; 1263 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in 1266 let isReturn=1, isTerminator=1, isBarrier=1, hasCtrlDep=1, hasSideEffects=1 in 1561 let isBarrier=1; [all …]
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D | Mips32r6InstrInfo.td | 301 bit isBarrier = 1; 398 bit isBarrier = 1; 407 bit isBarrier=1;
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D | MicroMips32r6InstrInfo.td | 267 bit isBarrier = 1; 282 let isBarrier = 1; 400 bit isBarrier = 1; 420 let isBarrier = 1;
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/external/llvm/utils/TableGen/ |
D | CodeGenInstruction.h | 232 bool isBarrier : 1; variable
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/external/llvm/lib/Target/PowerPC/ |
D | PPCInstr64Bit.td | 84 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in { 254 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 260 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 265 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 270 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 277 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 283 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 320 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
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D | PPCHazardRecognizers.cpp | 45 if (!SU->Preds[i].isNormalMemory() && !SU->Preds[i].isBarrier()) in isLoadAfterStore()
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/external/llvm/lib/Target/MSP430/ |
D | MSP430InstrInfo.cpp | 163 if (MI->isBranch() && !MI->isBarrier()) in isUnpredicatedTerminator()
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/external/llvm/lib/CodeGen/ |
D | MachineVerifier.cpp | 593 if (!MBB->empty() && MBB->back().isBarrier() && in visitMachineBasicBlockBefore() 618 } else if (!MBB->back().isBarrier()) { in visitMachineBasicBlockBefore() 649 } else if (MBB->back().isBarrier()) { in visitMachineBasicBlockBefore() 677 } else if (!MBB->back().isBarrier()) { in visitMachineBasicBlockBefore()
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/external/llvm/lib/Target/BPF/ |
D | BPFInstrInfo.td | 385 let isBranch = 1, isTerminator = 1, hasDelaySlot=0, isBarrier = 1 in { 433 let isReturn = 1, isTerminator = 1, hasDelaySlot=0, isBarrier = 1,
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/external/llvm/test/CodeGen/Hexagon/ |
D | barrier-flag.ll | 3 ; the "isBarrier" flag set on instructions that were not meant to have it.
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/external/llvm/lib/Target/Sparc/ |
D | SparcInstrInfo.td | 658 let isBarrier = 1; 695 let isTerminator = 1, isBarrier = 1, hasDelaySlot = 1, isBranch =1, 786 let isTerminator = 1, hasDelaySlot = 1, isBarrier = 1, 796 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1, 809 isBarrier = 1, rd = 0, DecoderMethod = "DecodeReturn" in { 830 let isBarrier = 1, isTerminator = 1, rd = 0b01000, rs1 = 0, simm13 = 5 in
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/external/llvm/lib/Target/Hexagon/ |
D | HexagonEarlyIfConv.cpp | 330 if (I->isBarrier()) in hasUncondBranch() 647 if (MI->isCall() || MI->isBarrier() || MI->isBranch()) in isSafeToSpeculate()
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D | HexagonVLIWPacketizer.cpp | 984 return MJ->isInlineAsm() || MJ->isBranch() || MJ->isBarrier() || in cannotCoexistAsymm() 1101 (J->isBranch() || J->isCall() || J->isBarrier()); in hasControlDependence()
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