| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDGPUInstrInfo.cpp | 227 bool AMDGPUInstrInfo::isPredicable(MachineInstr *MI) const { in isPredicable() function in AMDGPUInstrInfo
229 return MI->getDesc().isPredicable(); in isPredicable()
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| D | R600InstrInfo.h | 77 bool isPredicable(MachineInstr *MI) const;
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| D | R600InstrInfo.cpp | 360 R600InstrInfo::isPredicable(MachineInstr *MI) const in isPredicable() function in R600InstrInfo
362 return AMDGPUInstrInfo::isPredicable(MI); in isPredicable()
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| D | AMDGPUInstrInfo.h | 121 bool isPredicable(MachineInstr *MI) const;
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| /external/llvm/include/llvm/MC/ |
| D | MCInstrDesc.h | 264 bool isPredicable() const { return Flags & (1 << MCID::Predicable); } in isPredicable() function
538 if (isPredicable()) { in findFirstPredOperandIdx()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenInstruction.h | 141 bool isPredicable; variable
239 bool isPredicable : 1; variable
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| D | CodeGenInstruction.cpp | 29 isPredicable = false; in CGIOperandList()
97 isPredicable = true; in CGIOperandList()
310 isPredicable = Operands.isPredicable || R->getValueAsBit("isPredicable"); in CodeGenInstruction()
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| D | InstrInfoEmitter.cpp | 494 if (Inst.isPredicable) OS << "|(1ULL<<MCID::Predicable)"; in emitRecord()
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| /external/llvm/lib/Target/ARM/ |
| D | Thumb2SizeReduction.cpp | 708 if (!NewMCID.isPredicable()) in ReduceTo2Addr()
712 SkipPred = !NewMCID.isPredicable(); in ReduceTo2Addr()
804 if (!NewMCID.isPredicable()) in ReduceToNarrow()
808 SkipPred = !NewMCID.isPredicable(); in ReduceToNarrow()
862 if (!MCID.isPredicable() && NewMCID.isPredicable()) in ReduceToNarrow()
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| D | ARMBaseInstrInfo.h | 155 bool isPredicable(MachineInstr *MI) const override;
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstrInfo.cpp | 245 bool AMDGPUInstrInfo::isPredicable(MachineInstr *MI) const { in isPredicable() function in AMDGPUInstrInfo
247 return MI->getDesc().isPredicable(); in isPredicable()
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| D | AMDGPUInstrInfo.h | 130 bool isPredicable(MachineInstr *MI) const override;
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| D | R600InstrInfo.h | 173 bool isPredicable(MachineInstr *MI) const override;
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonExpandCondsets.cpp | 163 bool isPredicable(MachineInstr *MI);
750 bool HexagonExpandCondsets::isPredicable(MachineInstr *MI) { in isPredicable() function in HexagonExpandCondsets
751 if (HII->isPredicated(MI) || !HII->isPredicable(MI)) in isPredicable()
988 if (!DefI || !isPredicable(DefI)) in predicate()
1293 if (!RDef || !HII->isPredicable(RDef)) in coalesceSegments()
1299 if (!RDef || !HII->isPredicable(RDef)) in coalesceSegments()
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| D | HexagonInstrInfo.h | 207 bool isPredicable(MachineInstr *MI) const override;
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| D | HexagonInstrInfoV3.td | 24 let isCall = 1, hasSideEffects = 1, Defs = VolatileV3.Regs, isPredicable = 1,
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| D | HexagonEarlyIfConv.cpp | 448 if (!TII->isPredicable(Def1) || !TII->isPredicable(Def3)) in computePhiCost()
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| D | HexagonInstrInfoV4.td | 602 let isPredicable = 1 in
855 let isPredicable = 1 in
922 let isPredicable = 1, isNewValue = 1, opNewValue = 3 in
1064 let isPredicable = 1, isExtendable = 1, isExtentSigned = 1, opExtentBits = 8,
1258 let opNewValue = 2, opExtendable = 1, isExtentSigned = 1, isPredicable = 1 in
1409 let isPredicable = 1, hasSideEffects = 0, addrMode = PostInc, isNVStore = 1,
3263 let isBarrier = 1, isPredicable = 1 in
3282 Defs = [R29, R30, R31, PC], isPredicable = 0, isAsmParserOnly = 1 in {
3306 let hasSideEffects = 0, isPredicable = 1 in
3396 let opExtendable = 0, isPredicable = 1 in
[all …]
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| D | HexagonInstrInfo.td | 216 let isPredicable = 1 in
242 let isPredicable = 1 in
406 let opExtendable = 2, opExtentBits = 16, isPredicable = 1 in
529 let isPredicable = 1 in
580 let isPredicable = 1 in
623 isPredicated = 0, isPredicable = 1, isReMaterializable = 1 in
786 let isPredicable = 1, hasSideEffects = 0 in
827 let isPredicable = 1, hasSideEffects = 0 in
1437 isPredicable = 1,
1498 isPredicable = 1, hasSideEffects = 0, InputType = "reg" in
[all …]
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrInfo.h | 159 bool isPredicable(MachineInstr *MI) const override;
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.h | 246 bool isPredicable(MachineInstr *MI) const override;
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| /external/llvm/include/llvm/Target/ |
| D | TargetInstrInfo.h | 1048 virtual bool isPredicable(MachineInstr *MI) const { in isPredicable() function
1049 return MI->getDesc().isPredicable(); in isPredicable()
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| /external/llvm/lib/CodeGen/ |
| D | ImplicitNullChecks.cpp | 329 if (MI->mayLoad() && !MI->isPredicable() && BaseReg == PointerReg && in analyzeBlockForNullChecks()
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| D | TargetInstrInfo.cpp | 267 if (!MI->isPredicable()) in isUnpredicatedTerminator()
280 if (!MI->isPredicable()) in PredicateInstruction()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430InstrInfo.cpp | 165 if (!MI->isPredicable()) in isUnpredicatedTerminator()
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