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Searched refs:isUInt (Results 1 – 25 of 65) sorted by relevance

123

/external/llvm/lib/Target/SystemZ/MCTargetDesc/
DSystemZMCCodeEmitter.cpp153 assert(isUInt<4>(Base) && isUInt<12>(Disp)); in getBDAddr12Encoding()
163 assert(isUInt<4>(Base) && isInt<20>(Disp)); in getBDAddr20Encoding()
174 assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<4>(Index)); in getBDXAddr12Encoding()
185 assert(isUInt<4>(Base) && isInt<20>(Disp) && isUInt<4>(Index)); in getBDXAddr20Encoding()
197 assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<8>(Len)); in getBDLAddr12Len8Encoding()
208 assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<5>(Index)); in getBDVAddr12Encoding()
/external/llvm/lib/Target/SystemZ/
DSystemZTargetTransformInfo.cpp54 if (isUInt<32>(Imm.getZExtValue())) in getIntImmCost()
105 if (isUInt<32>(Imm.getZExtValue())) in getIntImmCost()
113 if (isUInt<32>(Imm.getZExtValue())) in getIntImmCost()
116 if (isUInt<32>(-Imm.getSExtValue())) in getIntImmCost()
131 if (isUInt<32>(Imm.getZExtValue())) in getIntImmCost()
144 if (isUInt<32>(~Imm.getZExtValue())) in getIntImmCost()
206 if (isUInt<32>(Imm.getZExtValue())) in getIntImmCost()
208 if (isUInt<32>(-Imm.getSExtValue())) in getIntImmCost()
DSystemZOperands.td282 return isUInt<1>(N->getZExtValue());
286 return isUInt<2>(N->getZExtValue());
290 return isUInt<3>(N->getZExtValue());
294 return isUInt<4>(N->getZExtValue());
300 return isUInt<4>(N->getZExtValue());
304 return isUInt<6>(N->getZExtValue());
312 return isUInt<8>(N->getZExtValue());
318 return isUInt<12>(N->getZExtValue());
326 return isUInt<16>(N->getZExtValue());
405 return isUInt<8>(N->getSExtValue());
[all …]
DSystemZInstrInfo.cpp626 isUInt<12>(MI->getOperand(2).getImm()) && in isSimpleBD12Move()
1160 if (isUInt<12>(Offset) && isUInt<12>(Offset2)) { in getOpcodeForOffset()
1269 return MI && isUInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CLIJ : 0; in getCompareAndBranch()
1271 return MI && isUInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CLGIJ : 0; in getCompareAndBranch()
DSystemZISelDAGToDAG.cpp366 return isUInt<12>(Val); in selectDisp()
484 return isUInt<12>(Val); in isValidDisp()
488 return !isUInt<12>(Val); in isValidDisp()
512 if (isUInt<12>(Disp)) in shouldUseLA()
/external/llvm/lib/Target/X86/AsmParser/
DX86AsmParserCommon.h17 (isUInt<16>(Value) && isInt<8>(static_cast<int16_t>(Value))); in isImmSExti16i8Value()
22 (isUInt<32>(Value) && isInt<8>(static_cast<int32_t>(Value))); in isImmSExti32i8Value()
34 return isUInt<8>(Value) || isInt<8>(Value); in isImmUnsignedi8Value()
/external/llvm/lib/Target/AMDGPU/
DSILoadStoreOptimizer.cpp150 if (isUInt<8>(EltOffset0) && isUInt<8>(EltOffset1)) in offsetsCanBeCombined()
158 return isUInt<8>(EltOffset0 / 64) && isUInt<8>(EltOffset1 / 64); in offsetsCanBeCombined()
238 assert((isUInt<8>(NewOffset0) && isUInt<8>(NewOffset1)) && in mergeRead2Pair()
334 assert((isUInt<8>(NewOffset0) && isUInt<8>(NewOffset1)) && in mergeWrite2Pair()
DAMDGPUISelDAGToDAG.cpp774 if ((OffsetBits == 16 && !isUInt<16>(Offset)) || in isDSOffsetLegal()
775 (OffsetBits == 8 && !isUInt<8>(Offset))) in isDSOffsetLegal()
803 if (isUInt<16>(ByteOffset)) { in SelectDS1Addr1Offset()
832 if (isUInt<16>(CAddr->getZExtValue())) { in SelectDS1Addr1Offset()
873 if (isUInt<8>(DWordOffset0)) { in SelectDS64Bit4ByteAligned()
900 if (isUInt<8>(DWordOffset0) && isUInt<8>(DWordOffset1)) { in SelectDS64Bit4ByteAligned()
920 return isUInt<12>(Imm->getZExtValue()); in isLegalMUBUFImmOffset()
962 } else if (isUInt<32>(C1->getZExtValue())) { in SelectMUBUF()
1100 isUInt<8>(EncodedOffset) : isUInt<20>(EncodedOffset); in isLegalSMRDImmOffset()
1123 if (!isUInt<32>(EncodedOffset) || !isUInt<32>(ByteOffset)) in SelectSMRDOffset()
[all …]
DSIISelLowering.cpp318 if (!isUInt<12>(AM.BaseOffs)) in isLegalMUBUFAddressingMode()
382 if (!isUInt<8>(AM.BaseOffs / 4)) in isLegalAddressingMode()
387 if (!isUInt<32>(AM.BaseOffs / 4)) in isLegalAddressingMode()
391 if (!isUInt<20>(AM.BaseOffs)) in isLegalAddressingMode()
415 if (!isUInt<16>(AM.BaseOffs)) in isLegalAddressingMode()
1731 return isUInt<12>(OffsetSize); in canFoldOffset()
1737 return isUInt<20>(OffsetSize); in canFoldOffset()
1739 return (OffsetSize % 4 == 0) && isUInt<8>(OffsetSize / 4); in canFoldOffset()
1744 return isUInt<16>(OffsetSize); in canFoldOffset()
2173 return isUInt<32>(Val) ? Val : -1; in analyzeImmediate()
DSIShrinkInstructions.cpp170 if (MovSrc.isImm() && isUInt<32>(MovSrc.getImm())) { in foldImmediates()
/external/llvm/lib/Target/Hexagon/
DHexagonOperands.td219 return isUInt<32>(v);
224 return isUInt<32>(v);
249 return isUInt<16>(v);
269 return isUInt<10>(v);
274 return isUInt<9>(v);
279 return isUInt<8>(v);
285 return isUInt<7>(Imm) && Imm > 0;
290 return isUInt<7>(v);
295 return isUInt<6>(v);
300 return isUInt<6>(v);
[all …]
DHexagonInstrInfo.cpp1155 return isUInt<6>(MI->getOperand(1).getImm()); in isPredicable()
1169 return isUInt<6>(MI->getOperand(2).getImm()); in isPredicable()
1188 return (OpCExtended[1] || isUInt<6>(MI->getOperand(1).getImm())) && in isPredicable()
2368 return isUInt<10>(Offset); in isValidOffset()
2445 return isUInt<6>(Offset); in isValidOffset()
2870 ((isUInt<5>(MI->getOperand(2).getImm())) || in getCompoundCandidateGroup()
3206 MI->getOperand(2).isImm() && isUInt<4>(MI->getOperand(2).getImm())) in getDuplexCandidateGroup()
3235 isUInt<3>(MI->getOperand(2).getImm())) in getDuplexCandidateGroup()
3314 MI->getOperand(1).isImm() && isUInt<4>(MI->getOperand(1).getImm())) in getDuplexCandidateGroup()
3350 MI->getOperand(2).isImm() && isUInt<1>(MI->getOperand(2).getImm())) in getDuplexCandidateGroup()
[all …]
/external/llvm/lib/Target/PowerPC/AsmParser/
DPPCAsmParser.cpp447 bool isU1Imm() const { return Kind == Immediate && isUInt<1>(getImm()); } in isU1Imm()
448 bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); } in isU2Imm()
449 bool isU3Imm() const { return Kind == Immediate && isUInt<3>(getImm()); } in isU3Imm()
450 bool isU4Imm() const { return Kind == Immediate && isUInt<4>(getImm()); } in isU4Imm()
451 bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); } in isU5Imm()
453 bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); } in isU6Imm()
455 isUInt<6>(getImm()) && in isU6ImmX2()
458 isUInt<7>(getImm()) && in isU7ImmX4()
461 isUInt<8>(getImm()) && in isU8ImmX8()
464 bool isU10Imm() const { return Kind == Immediate && isUInt<10>(getImm()); } in isU10Imm()
[all …]
/external/llvm/include/llvm/Support/
DMathExtras.h289 inline bool isUInt(uint64_t x) {
294 inline bool isUInt<8>(uint64_t x) {
298 inline bool isUInt<16>(uint64_t x) {
302 inline bool isUInt<32>(uint64_t x) {
310 return isUInt<N+S>(x) && (x % (1<<S) == 0);
/external/llvm/lib/IR/
DDataLayout.cpp254 if (!isUInt<24>(AddrSpace)) in parseSpecifier()
400 if (!isUInt<24>(bit_width)) in setAlignment()
402 if (!isUInt<16>(abi_align)) in setAlignment()
404 if (!isUInt<16>(pref_align)) in setAlignment()
/external/llvm/lib/Target/SystemZ/Disassembler/
DSystemZDisassembler.cpp127 if (!isUInt<N>(Imm)) in decodeUImmOperand()
135 if (!isUInt<N>(Imm)) in decodeSImmOperand()
210 assert(isUInt<N>(Imm) && "Invalid PC-relative offset"); in decodePCDBLOperand()
/external/llvm/lib/Target/AMDGPU/AsmParser/
DAMDGPUAsmParser.cpp1127 if (!isInt<32>(IntVal) && !isUInt<32>(IntVal)) { in parseOperand()
1414 return isImm() && isUInt<16>(getImm()); in isDSOffset()
1418 return isImm() && isUInt<8>(getImm()); in isDSOffset01()
1687 return isImm() && isUInt<12>(getImm()); in isMubufOffset()
1760 return isImm() && isUInt<8>(getImm()); in isSMRDOffset()
1766 return isImm() && !isUInt<8>(getImm()) && isUInt<32>(getImm()); in isSMRDLiteralOffset()
/external/jsoncpp/src/lib_json/
Djson_value.cpp578 JSON_ASSERT_MESSAGE(isUInt(), "LargestInt out of UInt range"); in asUInt()
581 JSON_ASSERT_MESSAGE(isUInt(), "LargestUInt out of UInt range"); in asUInt()
734 return isUInt() || in isConvertibleTo()
1111 bool Value::isUInt() const { in isUInt() function in Json::Value
1170 return isInt() || isUInt(); in isIntegral()
/external/llvm/lib/Target/Mips/
DMips16ISelLowering.cpp736 if (isUInt<8>(imm)) in emitFEXT_T8I8I16_ins()
738 else if ((!ImmSigned && isUInt<16>(imm)) || in emitFEXT_T8I8I16_ins()
752 if (isUInt<8>(Imm)) in Mips16WhichOp8uOr16simm()
DMips16InstrInfo.cpp211 if (isUInt<11>(FrameSize)) in makeFrame()
238 if (!isUInt<11>(FrameSize)) { in restoreFrame()
DMipsDSPInstrInfo.td15 def immZExt1 : ImmLeaf<i32, [{return isUInt<1>(Imm);}]>;
16 def immZExt2 : ImmLeaf<i32, [{return isUInt<2>(Imm);}]>;
17 def immZExt3 : ImmLeaf<i32, [{return isUInt<3>(Imm);}]>;
18 def immZExt4 : ImmLeaf<i32, [{return isUInt<4>(Imm);}]>;
19 def immZExt7 : ImmLeaf<i32, [{return isUInt<7>(Imm);}]>;
20 def immZExt8 : ImmLeaf<i32, [{return isUInt<8>(Imm);}]>;
21 def immZExt10 : ImmLeaf<i32, [{return isUInt<10>(Imm);}]>;
/external/llvm/lib/Target/SystemZ/InstPrinter/
DSystemZInstPrinter.cpp66 assert(isUInt<N>(Value) && "Invalid uimm argument"); in printUImmOperand()
/external/llvm/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp1641 bool Use32BitInsts = isUInt<32>(Mask); in SelectAndParts64()
1646 bool NeedsRotate = VRI.RLAmt || (VRI.Repl32 && !isUInt<32>(Mask)); in SelectAndParts64()
1690 if (VRI.RLAmt || (VRI.Repl32 && !isUInt<32>(Mask))) in SelectAndParts64()
1831 bool Use32BitInsts = isUInt<32>(Mask); in Select64()
1998 if (isUInt<16>(Imm)) in SelectCC()
2024 if (isInt32Immediate(RHS, Imm) && isUInt<16>(Imm)) in SelectCC()
2042 if (isUInt<16>(Imm)) in SelectCC()
2061 if (isUInt<32>(Imm)) { in SelectCC()
2071 if (isInt64Immediate(RHS.getNode(), Imm) && isUInt<16>(Imm)) in SelectCC()
3921 if (!isUInt<15>(Op32.getConstantOperandVal(0))) in PeepholePPC64ZExtGather()
[all …]
/external/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCInstrInfo.h185 return isUInt<N>(minConstant(MCI, Index)); in inRange()
/external/llvm/lib/Target/PowerPC/Disassembler/
DPPCDisassembler.cpp302 assert(isUInt<N>(Imm) && "Invalid immediate"); in decodeUImmOperand()
310 assert(isUInt<N>(Imm) && "Invalid immediate"); in decodeSImmOperand()

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