| /external/llvm/include/llvm/CodeGen/ |
| D | ValueTypes.h | 96 if (isVector()) in changeTypeToInteger()
128 bool isVector() const { in isVector() function
129 return isSimple() ? V.isVector() : isExtendedVector(); in isVector()
229 return isVector() ? getVectorElementType() : *this; in getScalarType()
235 assert(isVector() && "Invalid vector type!"); in getVectorElementType()
244 assert(isVector() && "Invalid vector type!"); in getVectorNumElements()
277 assert(isInteger() && !isVector() && "Invalid integer type!"); in getRoundIntegerType()
289 assert(isInteger() && !isVector() && "Invalid integer type!"); in getHalfSizedIntegerVT()
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| D | SelectionDAG.h | 729 assert(LHS.getValueType().isVector() == RHS.getValueType().isVector() &&
731 assert(LHS.getValueType().isVector() == VT.isVector() &&
744 assert(VT.isVector() == LHS.getValueType().isVector() &&
746 return getNode(Cond.getValueType().isVector() ? ISD::VSELECT : ISD::SELECT, DL, VT,
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| D | MachineValueType.h | 214 bool isVector() const { in isVector() function
303 return isVector() ? getVectorElementType() : *this; in getScalarType()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDILPeepholeOptimizer.cpp | 471 bool isVector = aType->isVectorTy(); in optimizeBitInsert() local
478 if (isVector) { in optimizeBitInsert()
488 if (isVector) { in optimizeBitInsert()
659 if (isVector) { name += "_v" + itostr(numEle) + "u32"; } else { name += "_u32"; } in optimizeBitInsert()
711 bool isVector = aType->isVectorTy(); in optimizeBitExtract() local
714 if (isVector) { in optimizeBitExtract()
723 if (isVector) { in optimizeBitExtract()
751 if (isVector) { in optimizeBitExtract()
819 if (isVector) { in optimizeBitExtract()
1007 bool isVector = aType->isVectorTy(); in expandSigned24BitOps() local
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| D | R600ExpandSpecialInstrs.cpp | 64 bool IsVector = TII->isVector(MI); in runOnMachineFunction()
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| D | R600InstrInfo.h | 55 bool isVector(const MachineInstr &MI) const;
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| /external/llvm/utils/TableGen/ |
| D | DAGISelEmitter.cpp | 88 if (LHSVT.isVector() != RHSVT.isVector()) in operator ()()
89 return RHSVT.isVector(); in operator ()()
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| D | DAGISelMatcher.cpp | 371 return !MVT(T2).isInteger() || MVT(T2).isVector(); in TypesAreContradictory()
374 return !MVT(T1).isInteger() || MVT(T1).isVector(); in TypesAreContradictory()
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| /external/clang/utils/ABITest/ |
| D | TypeGen.py | 117 def __init__(self, index, isVector, elementType, size): argument
118 if isVector:
124 self.isVector = isVector
127 if isVector:
135 if self.isVector:
144 if self.isVector:
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 143 HasVectors |= J->isVector(); in Run()
204 if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD) in LegalizeOp()
233 if (StVT.isVector() && ST->isTruncatingStore()) in LegalizeOp()
253 HasVectorValue |= J->isVector(); in LegalizeOp()
410 if (Op.getOperand(j).getValueType().isVector()) in Promote()
415 NVT.isVector() && NVT.getVectorElementType().isFloatingPoint()) in Promote()
425 (VT.isVector() && VT.getVectorElementType().isFloatingPoint() && in Promote()
426 NVT.isVector() && NVT.getVectorElementType().isFloatingPoint())) in Promote()
455 if (Op.getOperand(j).getValueType().isVector()) in PromoteINT_TO_FP()
738 assert(VT.isVector() && !Mask.getValueType().isVector() in ExpandSELECT()
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| D | LegalizeVectorTypes.cpp | 352 assert(N->getValueType(0).isVector() == in ScalarizeVecRes_SETCC()
353 N->getOperand(0).getValueType().isVector() && in ScalarizeVecRes_SETCC()
356 if (N->getValueType(0).isVector()) return ScalarizeVecRes_VSETCC(N); in ScalarizeVecRes_SETCC()
380 assert(N->getValueType(0).isVector() && in ScalarizeVecRes_VSETCC()
381 N->getOperand(0).getValueType().isVector() && in ScalarizeVecRes_VSETCC()
1158 assert(N->getValueType(0).isVector() && in SplitVecRes_SETCC()
1159 N->getOperand(0).getValueType().isVector() && in SplitVecRes_SETCC()
1479 assert(Mask.getValueType().isVector() && "VSELECT without a vector mask?"); in SplitVecOp_VSELECT()
1934 assert(N->getValueType(0).isVector() && in SplitVecOp_VSETCC()
1935 N->getOperand(0).getValueType().isVector() && in SplitVecOp_VSETCC()
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| D | SelectionDAG.cpp | 707 assert(!VT.isVector() && (VT.isInteger() || VT.isFloatingPoint()) && in VerifySDNode()
720 assert(N->getValueType(0).isVector() && "Wrong return type!"); in VerifySDNode()
1039 assert(!VT.isVector() && in getZeroExtendInReg()
1051 assert(VT.isVector() && "This DAG node is restricted to vector types."); in getAnyExtendVectorInReg()
1061 assert(VT.isVector() && "This DAG node is restricted to vector types."); in getSignExtendVectorInReg()
1071 assert(VT.isVector() && "This DAG node is restricted to vector types."); in getZeroExtendVectorInReg()
1131 if (VT.isVector() && TLI->getTypeAction(*getContext(), EltVT) == in getConstant()
1143 else if (NewNodesMustHaveLegalTypes && VT.isVector() && in getConstant()
1196 if (!VT.isVector()) in getConstant()
1207 if (VT.isVector()) { in getConstant()
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| D | DAGCombiner.cpp | 476 if (LHSTy.isVector()) in getShiftAmountTy()
1039 if (VT.isVector() || !VT.isInteger()) in PromoteIntBinOp()
1097 if (VT.isVector() || !VT.isInteger()) in PromoteIntShiftOp()
1141 if (VT.isVector() || !VT.isInteger()) in PromoteExtend()
1170 if (VT.isVector() || !VT.isInteger()) in PromoteLoad()
1644 if (VT.isVector()) { in visitADD()
1733 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) in visitADD()
1738 VT.isInteger() && !VT.isVector() && DAG.haveNoCommonBitsSet(N0, N1)) in visitADD()
1856 if (!VT.isVector()) in tryFoldToZero()
1869 if (VT.isVector()) { in visitSUB()
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| D | LegalizeTypesGeneric.cpp | 106 if (InVT.isVector() && OutVT.isInteger()) { in ExpandRes_BITCAST()
346 if (N->getValueType(0).isVector()) { in ExpandOp_BITCAST()
532 if (Cond.getValueType().isVector()) { in SplitRes_SELECT()
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| /external/parameter-framework/upstream/parameter/ |
| D | ElementHandle.cpp | 155 struct isVector : std::false_type struct
159 struct isVector<std::vector<T>> : std::true_type struct
226 if (not checkGetValidity(isVector<T>::value, error)) { in getAs()
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| /external/clang/include/clang/AST/ |
| D | APValue.h | 187 bool isVector() const { return Kind == Vector; } in isVector() function
259 assert(isVector() && "Invalid accessor"); in getVectorElt()
267 assert(isVector() && "Invalid accessor"); in getVectorLength()
356 assert(isVector() && "Invalid accessor"); in setVector()
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| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMELFStreamer.cpp | 74 bool isVector) override;
138 bool isVector) { in emitRegSave() argument
140 if (isVector) in emitRegSave()
370 bool isVector) override;
435 void emitRegSave(const SmallVectorImpl<unsigned> &RegList, bool isVector);
644 bool isVector) { in emitRegSave() argument
645 getStreamer().emitRegSave(RegList, isVector); in emitRegSave()
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| D | ARMTargetStreamer.cpp | 54 bool isVector) {} in emitRegSave() argument
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| /external/llvm/lib/Target/AMDGPU/ |
| D | R600EmitClauseMarkers.cpp | 59 if(TII->isVector(*MI) || in OccupiedDwords()
77 if (TII->isVector(*MI) || TII->isCubeOp(MI->getOpcode())) in isALU()
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| D | CaymanInstructions.td | 32 let isVector = 1 in {
47 } // End isVector = 1
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| D | R600ISelLowering.cpp | 1395 if (ValueVT.isVector()) { in LowerSTORE()
1496 if (LoadNode->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS && VT.isVector()) { in LowerLOAD()
1525 if (VT.isVector()) { in LowerLOAD()
1541 if (!VT.isVector()) { in LowerLOAD()
1562 assert(!MemVT.isVector() && (MemVT == MVT::i16 || MemVT == MVT::i8)); in LowerLOAD()
1588 if (VT.isVector()) { in LowerLOAD()
1662 if (!VT.isVector() && MemVT.isVector()) { in LowerFormalArguments()
1717 if (!VT.isVector()) in getSetCCResultType()
2084 if (ParentNode->getValueType(0).isVector()) in FoldOperand()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZCallingConv.h | 36 return ArgVT.isVector() && ArgVT.getStoreSize() <= 8; in IsShortVectorType()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64AsmPrinter.cpp | 94 const TargetRegisterClass *RC, bool isVector,
239 bool isVector, raw_ostream &O) { in printAsmRegInClass() argument
247 RegToPrint, isVector ? AArch64::vreg : AArch64::NoRegAltName); in printAsmRegInClass()
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| /external/clang/utils/TableGen/ |
| D | NeonEmitter.cpp | 173 bool isVector() const { return NumVectors > 0; } in isVector() function in __anonb7c1857d0111::Type
212 assert(isVector()); in makeOneVector()
568 if (isVector()) in str()
1034 if (T.isHalf() && T.isVector() && !T.isScalarForMangling()) in getBuiltinTypeStr()
1229 if (!NewV.getType().isVector() || NewV.getType().getNumElements() == 1) in emitArgumentReversal()
1241 if (!getReturnType().isVector() || getReturnType().isVoid() || in emitReturnReversal()
1356 if (CastToType.isVector()) { in emitBodyAsBuiltinCall()
1690 assert_with_loc(T.isVector(), "dup() used but default type is scalar!"); in emitDagDup()
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 60 unsigned matchRegisterNameAlias(StringRef Name, bool isVector);
177 bool isVector; member
920 bool isReg() const override { return Kind == k_Register && !Reg.isVector; } in isReg()
921 bool isVectorReg() const { return Kind == k_Register && Reg.isVector; } in isVectorReg()
923 return Kind == k_Register && Reg.isVector && in isVectorRegLo()
928 return Kind == k_Register && !Reg.isVector && in isGPR32as64()
932 return Kind == k_Register && !Reg.isVector && in isWSeqPair()
937 return Kind == k_Register && !Reg.isVector && in isXSeqPair()
943 return Kind == k_Register && !Reg.isVector && in isGPR64sp0()
1640 CreateReg(unsigned RegNum, bool isVector, SMLoc S, SMLoc E, MCContext &Ctx) { in CreateReg() argument
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