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Searched refs:movw (Results 1 – 25 of 164) sorted by relevance

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/external/llvm/test/MC/ARM/
Dtarget-expressions.s18 movw r0, :lower16:function
21 movw r1, #:lower16:function
24 movw r2, :lower16:deadbeat
27 movw r3, #:lower16:deadbeat
30 movw r4, :lower16:0xD1510D6E
33 movw r5, #:lower16:0xD1510D6E
36 movw r0, :lower16:external
39 movw r1, #:lower16:external
42 movw r2, #:lower16:(16 + 16)
45 movw r3, :lower16:(16 + 16)
[all …]
Darm_fixups.s13 movw r9, :lower16:(_foo)
16 @ CHECK: movw r9, :lower16:_foo @ encoding: [A,0x90'A',0b0000AAAA,0xe3]
18 @ CHECK-BE: movw r9, :lower16:_foo @ encoding: [0xe3,0b0000AAAA,0x90'A',A]
20 @ CHECK: movw r9, :lower16:_foo @ encoding: [A,0x90'A',0b0000AAAA,0xe3]
22 @ CHECK-BE: movw r9, :lower16:_foo @ encoding: [0xe3,0b0000AAAA,0x90'A',A]
31 @ CHECK: movw r2, :lower16:fred @ encoding: [A,0x20'A',0b0000AAAA,0xe3]
33 @ CHECK-BE: movw r2, :lower16:fred @ encoding: [0xe3,0b0000AAAA,0x20'A',A]
Dthumb2be-movw-encoding.s4 movw r9, :lower16:(_bar) label
5 @ CHECK-LE: movw r9, :lower16:_bar @ encoding: [0x40'A',0xf2'A',0b0000AAAA,0x09]
7 @ CHECK-BE: movw r9, :lower16:_bar @ encoding: [0xf2,0b0100AAAA,0x09'A',A]
/external/llvm/test/CodeGen/ARM/
Dfast-isel-call.ll12 ; movw/movt or constant pool loads. Different platforms will select
44 ; ARM: movw r2, #1
72 ; ARM: movw r1, #255
74 ; ARM: movw r1, #65535
75 ; THUMB: movw r1, #65535
98 ; ARM: movw [[R0:l?r[0-9]*]], #0
99 ; ARM: movw [[R1:l?r[0-9]*]], #248
100 ; ARM: movw [[R2:l?r[0-9]*]], #187
101 ; ARM: movw [[R3:l?r[0-9]*]], #28
102 ; ARM: movw [[R4:l?r[0-9]*]], #40
[all …]
Dpr18364-movw.ll9 ; V5-NOT: movw
10 ; V6-NOT: movw
11 ; V6T2: movw
12 ; V7: movw
25 ; V5-NOT: movw
26 ; V6-NOT: movw
27 ; V6T2: movw
28 ; V7: movw
Dmovt-movw-global.ll10 ; EABI: movw r0, :lower16:foo
13 ; IOS: movw r0, :lower16:L_foo$non_lazy_ptr
16 ; IOS-PIC: movw r0, :lower16:(L_foo$non_lazy_ptr-(LPC0_0+8))
19 ; IOS-STATIC: movw r0, :lower16:_foo
26 ; EABI: movw r1, :lower16:foo
29 ; IOS: movw r1, :lower16:L_foo$non_lazy_ptr
32 ; IOS-PIC: movw r1, :lower16:(L_foo$non_lazy_ptr-(LPC1_0+8))
35 ; IOS-STATIC: movw r1, :lower16:_foo
Dfast-isel-intrinsic.ll9 ; movw/movt or constant pool loads. Different platforms will select
17 ; ARM: {{(movw r0, :lower16:_?message1)|(ldr r0, .LCPI)}}
20 ; ARM: movw r1, #64
21 ; ARM: movw r2, #10
25 ; ARM-LONG: {{(movw r3, :lower16:L_memset\$non_lazy_ptr)|(ldr r3, .LCPI)}}
30 ; THUMB: {{(movw r0, :lower16:_?message1)|(ldr.n r0, .LCPI)}}
38 ; THUMB-LONG: movw r3, :lower16:L_memset$non_lazy_ptr
50 ; ARM: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr r0, .LCPI)}}
55 ; ARM: movw r2, #17
61 ; ARM-LONG: {{(movw r3, :lower16:L_memcpy\$non_lazy_ptr)|(ldr r3, .LCPI)}}
[all …]
Dshifter_operand.ll68 ; CHECK: movw r2, #63767
80 ; CHECK: movw r2, #63767
92 ; CHECK: movw r2, #63767
104 ; CHECK: movw r2, #63767
116 ; CHECK: movw r2, #63767
128 ; CHECK: movw r2, #63767
140 ; CHECK: movw r2, #63767
154 ; CHECK: movw r2, #63767
168 ; CHECK: movw r2, #63767
182 ; CHECK: movw r2, #63767
[all …]
D2011-11-29-128bitArithmetics.ll9 ; CHECK: movw r1, :lower16:{{.*}}
32 ; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
63 ; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
94 ; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
125 ; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
156 ; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
187 ; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
219 ; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
253 ; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
276 ; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
[all …]
Datomic-ops-v8.ll16 ; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8
39 ; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var16
62 ; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var32
85 ; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var64
112 ; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8
135 ; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var16
158 ; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var32
181 ; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var64
208 ; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8
231 ; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var16
[all …]
D2012-10-04-AAPCS-byval-align8.ll29 ; CHECK: movw [[BASE:r[0-9]+]], :lower16:static_val
33 ; CHECK: movw r0, #555
56 ; CHECK: movw [[BASE:r[0-9]+]], :lower16:static_val
60 ; CHECK: movw r0, #555
/external/llvm/test/CodeGen/X86/
D3addr-16bit.ll9 ; 32BIT: movw 20(%esp), %ax
10 ; 32BIT-NOT: movw %ax, %cx
14 ; 64BIT-NOT: movw %si, %ax
31 ; 32BIT: movw 20(%esp), %ax
32 ; 32BIT-NOT: movw %ax, %cx
36 ; 64BIT-NOT: movw %si, %ax
56 ; 32BIT: movw 20(%esp), %ax
57 ; 32BIT-NOT: movw %ax, %cx
61 ; 64BIT-NOT: movw %si, %ax
78 ; 32BIT: movw 16(%esp), %ax
[all …]
Dstore-narrow.ll50 ; X64: movw %si, (%rdi)
53 ; X32: movw 8(%esp), %ax
54 ; X32: movw %ax, (%{{.*}})
67 ; X64: movw %si, 2(%rdi)
70 ; X32: movw 8(%esp), %[[REG:[abcd]]]x
71 ; X32: movw %[[REG]]x, 2(%{{.*}})
84 ; X64: movw %si, 2(%rdi)
87 ; X32: movw 8(%esp), %[[REG:[abcd]]]x
88 ; X32: movw %[[REG]]x, 2(%{{.*}})
Dhalf.ll10 ; CHECK: movw (%rdi), [[TMP:%[a-z0-9]+]]
11 ; CHECK: movw [[TMP]], (%rsi)
27 ; CHECK: movw %si, (%rdi)
102 ; CHECK-LIBCALL-NEXT: movw %ax, ([[ADDR]])
109 ; CHECK-F16C-NEXT: movw %ax, (%rsi)
178 ; CHECK-LIBCALL-NEXT: movw %ax, ([[ADDR]])
182 ; CHECK-F16C-NEXT: movw %ax, (%rsi)
241 ; CHECK: movw
242 ; CHECK: movw
243 ; CHECK: movw
[all …]
Dasm-modifier.ll9 ; CHECK: movw %gs:6, %ax
10 …%asmtmp.i = tail call i16 asm "movw\09%gs:${1:a}, ${0:w}", "=r,ir,~{dirflag},~{fpsr},~{flags}"(i32…
18 ; CHECK: movw %gs:(%eax), %ax
19 …%asmtmp = tail call i16 asm "movw\09%gs:${1:a}, ${0:w}", "=r,ir,~{dirflag},~{fpsr},~{flags}"(i32 %…
Dextract-store.ll19 ; AVX-NOT: movw
20 ; SSE41-NOT: movw
41 ; AVX-NOT: movw
42 ; SSE41-NOT: movw
Dpr14088.ll22 ; We were miscompiling this and using %ax instead of %cx in the movw
25 ; movw %cx, (%rsi)
30 ; CHECK: movw %ax, (%rsi)
/external/llvm/test/MC/Disassembler/X86/
Dmoffs.txt15 # 16: movw 0x5a5a, %ax # encoding: [0xa1,0x5a,0x5a]
20 # 16: movw 0x5a5a5a5a, %ax # encoding: [0x67,0xa1,0x5a,0x5a,0x5a,0x5a]
26 # 32: movw 0x5a5a5a5a, %ax # encoding: [0x66,0xa1,0x5a,0x5a,0x5a,0x5a]
31 # 32: movw 0x5a5a, %ax # encoding: [0x67,0x66,0xa1,0x5a,0x5a]
32 # 64: movw 0x5a5a5a5a, %ax # encoding: [0x67,0x66,0xa1,0x5a,0x5a,0x5a,0x5a]
36 # 32: movw 0x5a5a, %ax # encoding: [0x67,0x66,0xa1,0x5a,0x5a]
37 # 64: movw 0x5a5a5a5a, %ax # encoding: [0x67,0x66,0xa1,0x5a,0x5a,0x5a,0x5a]
41 # 32: movw %es:0x5a5a, %ax # encoding: [0x67,0x66,0x26,0xa1,0x5a,0x5a]
42 # 64: movw %es:0x5a5a5a5a, %ax # encoding: [0x67,0x66,0x26,0xa1,0x5a,0x5a,0x5a,0x5a]
57 # 16: movw %ax, 0x5a5a # encoding: [0xa3,0x5a,0x5a]
[all …]
/external/libunwind/src/x86/
Dgetcontext-freebsd.S50 movw %fs, %cx
52 movw %gs, %cx
54 movw %ds, %cx
56 movw %es, %cx
58 movw %ss, %cx
60 movw %cs, %cx
/external/libunwind/src/x86_64/
Dgetcontext.S78 movw %cs, UC_MCONTEXT_CS(%rdi)
79 movw %ss, UC_MCONTEXT_SS(%rdi)
83 movw %ds, UC_MCONTEXT_DS(%rdi)
84 movw %es, UC_MCONTEXT_ES(%rdi)
85 movw %fs, UC_MCONTEXT_FS(%rdi)
86 movw %gs, UC_MCONTEXT_GS(%rdi)
/external/valgrind/coregrind/m_dispatch/
Ddispatch-arm-linux.S104 movw r1, #VG_TRC_INVARIANT_FAILED
105 movw r2, #0
157 movw r1, #:lower16:vgPlain_stats__n_xindirs_32
165 movw r1, #VG_TT_FAST_MASK // r1 = VG_TT_FAST_MASK
166 movw r4, #:lower16:VG_(tt_fast)
182 movw r1, #:lower16:vgPlain_stats__n_xindir_misses_32
/external/llvm/test/CodeGen/ARM/Windows/
Dmovw-movt-relocations.ll19 ; CHECK-WINDOWS: movw r[[i:[0-4]]], :lower16:i
21 ; CHECK-WINDOWS: movw r[[j:[0-4]]], :lower16:j
24 ; CHECK-EABI: movw r[[i:[0-4]]], :lower16:i
25 ; CHECK-EABI: movw r[[j:[0-4]]], :lower16:j
Ddllimport.ll16 ; CHECK: movw r0, :lower16:__imp_var
28 ; CHECK: movw r0, :lower16:ext
38 ; CHECK: movw r0, :lower16:__imp_var
49 ; CHECK: movw r0, :lower16:__imp_external
Dchkstk.ll14 ; CHECK-DEFAULT-CODE-MODEL: movw r4, #1024
19 ; CHECK-LARGE-CODE-MODEL: movw r12, :lower16:__chkstk
21 ; CHECK-LARGE-CODE-MODEL: movw r4, #1024
/external/llvm/test/MC/X86/
Daddress-size.s14 movw $0x1234, (%si)
18 movw $0x1234, 0x5678(%bp)

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