| /external/llvm/lib/Target/AMDGPU/ |
| D | R600ClauseMergePass.cpp | 99 CFAlu->getOperand(CntIdx).setImm(getCFAluSize(CFAlu) + getCFAluSize(MI)); in cleanPotentialDisabledCFAlu()
150 RootCFAlu->getOperand(Mode0Idx).setImm( in mergeIfPossible()
152 RootCFAlu->getOperand(KBank0Idx).setImm( in mergeIfPossible()
154 RootCFAlu->getOperand(KBank0LineIdx).setImm( in mergeIfPossible()
158 RootCFAlu->getOperand(Mode1Idx).setImm( in mergeIfPossible()
160 RootCFAlu->getOperand(KBank1Idx).setImm( in mergeIfPossible()
162 RootCFAlu->getOperand(KBank1LineIdx).setImm( in mergeIfPossible()
165 RootCFAlu->getOperand(CntIdx).setImm(CumuledInsts); in mergeIfPossible()
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| D | R600InstrInfo.cpp | 791 PredSet->getOperand(2).setImm(Cond[1].getImm()); in InsertBranch()
807 PredSet->getOperand(2).setImm(Cond[1].getImm()); in InsertBranch()
960 MO.setImm(OPCODE_IS_NOT_ZERO_INT); in ReverseBranchCondition()
963 MO.setImm(OPCODE_IS_ZERO_INT); in ReverseBranchCondition()
966 MO.setImm(OPCODE_IS_NOT_ZERO); in ReverseBranchCondition()
969 MO.setImm(OPCODE_IS_ZERO); in ReverseBranchCondition()
1009 MI->getOperand(8).setImm(0); in PredicateInstruction()
1298 MIB->getOperand(20).setImm(0); in buildSlotOfVectorInstruction()
1331 MI->getOperand(Idx).setImm(Imm); in setImmOperand()
1410 FlagOp.setImm(1); in addFlag()
[all …]
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| D | R600Packetizer.cpp | 231 MI->getOperand(LastOp).setImm(Bit); in setIsLastBit()
309 MI->getOperand(Op).setImm(BS[i]); in addToPacket()
313 MI->getOperand(Op).setImm(BS.back()); in addToPacket()
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| D | R600ControlFlowFinalizer.cpp | 429 ClauseHead->getOperand(7).setImm(ClauseContent.size() - 1); in MakeALUClause()
449 Clause.first->getOperand(0).setImm(0); in EmitALUClause()
461 MI->getOperand(0).setImm(Addr + MI->getOperand(0).getImm()); in CounterPropagateAddr()
602 IfOrElseInst->getOperand(1).setImm(1); in runOnMachineFunction()
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| D | AMDILCFGStructurizer.cpp | 450 .setImm(OPCODE_IS_NOT_ZERO_INT); in reversePredicateSetter()
454 .setImm(OPCODE_IS_ZERO_INT); in reversePredicateSetter()
458 .setImm(OPCODE_IS_NOT_ZERO); in reversePredicateSetter()
462 .setImm(OPCODE_IS_ZERO); in reversePredicateSetter()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | R600InstrInfo.cpp | 277 PredSet->getOperand(2).setImm(Cond[1].getImm()); in InsertBranch()
288 PredSet->getOperand(2).setImm(Cond[1].getImm()); in InsertBranch()
409 MO.setImm(OPCODE_IS_NOT_ZERO_INT); in ReverseBranchCondition()
412 MO.setImm(OPCODE_IS_ZERO_INT); in ReverseBranchCondition()
415 MO.setImm(OPCODE_IS_NOT_ZERO); in ReverseBranchCondition()
418 MO.setImm(OPCODE_IS_ZERO); in ReverseBranchCondition()
502 FlagOp.setImm(FlagOp.getImm() | (Flag << (NUM_MO_FLAGS * Operand))); in addFlag()
511 FlagOp.setImm(InstFlags); in clearFlag()
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyRegisterInfo.cpp | 71 MI.getOperand(1).setImm(FrameOffset); in eliminateFrameIndex()
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| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCInstrInfo.cpp | 626 Operand.setImm(Operand.getImm() | innerLoopMask); in setInnerLoop()
632 Operand.setImm(Operand.getImm() | memReorderDisabledMask); in setMemReorderDisabled()
639 Operand.setImm(Operand.getImm() | memStoreReorderEnabledMask); in setMemStoreReorderEnabled()
646 Operand.setImm(Operand.getImm() | outerLoopMask); in setOuterLoop()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCMIPeephole.cpp | 156 MI.getOperand(3).setImm(3 - Immed); in simplifyCode()
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| D | PPCVSXSwapRemoval.cpp | 813 MI->getOperand(1).setImm(EltNo); in handleSpecialSwappables()
835 MI->getOperand(3).setImm(Selector); in handleSpecialSwappables()
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| D | PPCInstrInfo.cpp | 400 MI->getOperand(4).setImm((ME+1) & 31); in commuteInstructionImpl()
401 MI->getOperand(5).setImm((MB-1) & 31); in commuteInstructionImpl()
1181 Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0); in ReverseBranchCondition()
1184 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm())); in ReverseBranchCondition()
1768 PredsToUpdate[i].first->setImm(PredsToUpdate[i].second); in optimizeCompareInstr()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMMCInstLower.cpp | 158 MCOp.setImm(Enc); in LowerARMMachineInstrToMCInst()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZElimCompare.cpp | 291 AlterMasks[I]->setImm(CCValues); in adjustCCMasksForInstr()
294 AlterMasks[I + 1]->setImm((CCMask & ReusableCCMask) | in adjustCCMasksForInstr()
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| D | SystemZInstrInfo.cpp | 70 LowOffsetOp.setImm(LowOffsetOp.getImm() + 8); in splitMove()
99 OffsetMO.setImm(Offset); in splitAdjDynAlloc()
115 MI->getOperand(1).setImm(uint32_t(MI->getOperand(1).getImm())); in expandRIPseudo()
364 Cond[1].setImm(Cond[1].getImm() ^ Cond[0].getImm()); in ReverseBranchCondition()
1042 MI->getOperand(5).setImm(MI->getOperand(5).getImm() ^ 32); in expandPostRAPseudo()
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| D | SystemZShortenInst.cpp | 96 MI.getOperand(1).setImm(Imm >> 16); in shortenIIF()
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| /external/llvm/include/llvm/MC/ |
| D | MCInst.h | 78 void setImm(int64_t Val) { in setImm() function
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineOperand.h | 508 void setImm(int64_t immVal) { in setImm() function
581 Op.setImm(Val); in CreateImm()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 184 Cond[0].setImm(AArch64CC::getInvertedCondCode(CC)); in ReverseBranchCondition()
191 Cond[1].setImm(AArch64::CBNZW); in ReverseBranchCondition()
194 Cond[1].setImm(AArch64::CBZW); in ReverseBranchCondition()
197 Cond[1].setImm(AArch64::CBNZX); in ReverseBranchCondition()
200 Cond[1].setImm(AArch64::CBZX); in ReverseBranchCondition()
203 Cond[1].setImm(AArch64::TBNZW); in ReverseBranchCondition()
206 Cond[1].setImm(AArch64::TBZW); in ReverseBranchCondition()
209 Cond[1].setImm(AArch64::TBNZX); in ReverseBranchCondition()
212 Cond[1].setImm(AArch64::TBZX); in ReverseBranchCondition()
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsMCCodeEmitter.cpp | 63 Inst.getOperand(2).setImm(Shift); in LowerLargeShift()
104 InstIn.getOperand(2).setImm(pos - 32); in LowerDextDins()
110 InstIn.getOperand(3).setImm(size - 32); in LowerDextDins()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonPeephole.cpp | 320 Dst.setImm(Src.getImm()); in ChangeOpInto()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsInstrInfo.cpp | 173 Cond[0].setImm(getOppositeBranchOpc(Cond[0].getImm())); in ReverseBranchCondition()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430InstrInfo.cpp | 155 Cond[0].setImm(CC); in ReverseBranchCondition()
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| /external/llvm/lib/CodeGen/ |
| D | LiveDebugValues.cpp | 331 MI->getOperand(1).setImm(DMI->getOperand(1).getImm()); in join()
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| /external/llvm/lib/Target/X86/ |
| D | X86CallFrameOptimization.cpp | 453 FrameSetup->getOperand(1).setImm(Context.ExpectedDist); in adjustCallSequence()
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreInstrInfo.cpp | 409 Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Cond[0].getImm())); in ReverseBranchCondition()
|