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/external/llvm/test/CodeGen/PowerPC/
Dvec_cmp.ll14 %sext = sext <2 x i1> %cmp to <2 x i8>
15 ret <2 x i8> %sext
23 %sext = sext <4 x i1> %cmp to <4 x i8>
24 ret <4 x i8> %sext
32 %sext = sext <8 x i1> %cmp to <8 x i8>
33 ret <8 x i8> %sext
43 %sext = sext <16 x i1> %cmp to <16 x i8>
44 ret <16 x i8> %sext
52 %sext = sext <16 x i1> %cmp to <16 x i8>
53 ret <16 x i8> %sext
[all …]
/external/llvm/test/CodeGen/X86/
Dsetcc-combine.ll10 %sext = sext <4 x i1> %cmp to <4 x i32>
11 %cmp1 = icmp eq <4 x i32> %sext, zeroinitializer
13 %1 = sext i1 %0 to i32
24 %sext = sext <4 x i1> %cmp to <4 x i32>
25 %cmp1 = icmp ne <4 x i32> %sext, zeroinitializer
27 %1 = sext i1 %0 to i32
37 %sext = sext <4 x i1> %cmp to <4 x i32>
38 %cmp1 = icmp sle <4 x i32> %sext, zeroinitializer
40 %1 = sext i1 %0 to i32
51 %sext = sext <4 x i1> %cmp to <4 x i32>
[all …]
Dpmovsx-inreg.ll10 %sext = sext <2 x i8> %wide.load35 to <2 x i64>
12 store <2 x i64> %sext, <2 x i64>* %out, align 8
27 %sext = sext <4 x i8> %wide.load35 to <4 x i64>
29 store <4 x i64> %sext, <4 x i64>* %out, align 8
38 %sext = sext <4 x i8> %wide.load35 to <4 x i32>
40 store <4 x i32> %sext, <4 x i32>* %out, align 8
55 %sext = sext <8 x i8> %wide.load35 to <8 x i32>
57 store <8 x i32> %sext, <8 x i32>* %out, align 8
66 %sext = sext <8 x i8> %wide.load35 to <8 x i16>
68 store <8 x i16> %sext, <8 x i16>* %out, align 8
[all …]
Dshrink-compare.ll115 %sext = sext i8 %x to i32
116 %cmp = icmp eq i32 %sext, 1
131 %sext = sext i8 %x to i32
132 %cmp = icmp eq i32 %sext, 47
147 %sext = sext i8 %x to i32
148 %cmp = icmp eq i32 %sext, 127
163 %sext = sext i8 %x to i32
164 %cmp = icmp eq i32 %sext, -1
179 %sext = sext i8 %x to i32
180 %cmp = icmp eq i32 %sext, -2
[all …]
/external/llvm/test/Analysis/BasicAA/
Dq.bad.ll8 %sext.1 = sext i8 255 to i16
9 %sext.zext.1 = zext i16 %sext.1 to i64
10 %sext.2 = sext i8 255 to i32
11 %sext.zext.2 = zext i32 %sext.2 to i64
12 %a = getelementptr inbounds i8, i8* %mem, i64 %sext.zext.1
13 %b = getelementptr inbounds i8, i8* %mem, i64 %sext.zext.2
19 ; %a and %b only PartialAlias as, although they're both zext(sext(%num)) they'll extend the sign by…
22 %sext.1 = sext i8 %num to i16
23 %sext.zext.1 = zext i16 %sext.1 to i64
24 %sext.2 = sext i8 %num to i32
[all …]
/external/llvm/test/CodeGen/AMDGPU/
Dsign_extend.ll9 %sext = sext i1 %cmp to i32
10 store i32 %sext, i32 addrspace(1)* %out, align 4
21 %sext = sext i32 %add to i64
22 store i64 %sext, i64 addrspace(1)* %out, align 8
33 %sext = sext i1 %cmp to i64
34 store i64 %sext, i64 addrspace(1)* %out, align 8
42 %sext = sext i32 %a to i64
43 store i64 %sext, i64 addrspace(1)* %out, align 8
52 %sext = sext i32 %val to i64
53 store i64 %sext, i64 addrspace(1)* %out, align 8
[all …]
Dllvm.AMDGPU.class.ll19 %sext = sext i1 %result to i32
20 store i32 %sext, i32 addrspace(1)* %out, align 4
35 %sext = sext i1 %result to i32
36 store i32 %sext, i32 addrspace(1)* %out, align 4
51 %sext = sext i1 %result to i32
52 store i32 %sext, i32 addrspace(1)* %out, align 4
68 %sext = sext i1 %result to i32
69 store i32 %sext, i32 addrspace(1)* %out, align 4
81 %sext = sext i1 %result to i32
82 store i32 %sext, i32 addrspace(1)* %out, align 4
[all …]
Dsetcc64.ll15 %1 = sext i1 %0 to i32
25 %1 = sext i1 %0 to i32
35 %1 = sext i1 %0 to i32
45 %1 = sext i1 %0 to i32
55 %1 = sext i1 %0 to i32
66 %1 = sext i1 %0 to i32
76 %1 = sext i1 %0 to i32
87 %1 = sext i1 %0 to i32
99 %1 = sext i1 %0 to i32
110 %1 = sext i1 %0 to i32
[all …]
/external/llvm/test/Analysis/ScalarEvolution/
Dinfer-prestart-no-wrap.ll3 define void @infer.sext.0(i1* %c, i32 %start) {
4 ; CHECK-LABEL: Classifying expressions for: @infer.sext.0
12 %idx.inc.sext = sext i32 %idx.inc to i64
13 ; CHECK: %idx.inc.sext = sext i32 %idx.inc to i64
14 ; CHECK-NEXT: --> {(1 + (sext i32 %start to i64))<nsw>,+,1}<nsw><%loop>
32 %idx.inc.sext = zext i32 %idx.inc to i64
33 ; CHECK: %idx.inc.sext = zext i32 %idx.inc to i64
43 define void @infer.sext.1(i32 %start, i1* %c) {
44 ; CHECK-LABEL: Classifying expressions for: @infer.sext.1
52 %idx.sext = sext i32 %idx to i64
[all …]
Dscev-prestart-nowrap.ll16 ; %postinc.sext = sext(INT_SMIN) = i64 INT32_SMIN
34 %postinc.sext = sext i32 %postinc to i64
35 ; CHECK: %postinc.sext = sext i32 %postinc to i64
36 ; CHECK-NEXT: --> {(sext i32 (1 + %start) to i64),+,1}<nsw><%loop>
49 ret i64 %postinc.sext
62 %postinc.sext = sext i32 %postinc to i64
63 ; CHECK: %postinc.sext = sext i32 %postinc to i64
64 ; CHECK-NEXT: --> {(sext i32 (1 + %start) to i64),+,1}<nsw><%loop>
81 ret i64 %postinc.sext
Dsext-iv-1.ll4 ; CHECK: --> (sext i{{.}} {{{.*}},+,{{.*}}}<%bb1> to i64)
5 ; CHECK: --> (sext i{{.}} {{{.*}},+,{{.*}}}<%bb1> to i64)
6 ; CHECK: --> (sext i{{.}} {{{.*}},+,{{.*}}}<%bb1> to i64)
7 ; CHECK: --> (sext i{{.}} {{{.*}},+,{{.*}}}<%bb1> to i64)
8 ; CHECK: --> (sext i{{.}} {{{.*}},+,{{.*}}}<%bb1> to i64)
9 ; CHECK-NOT: --> (sext
11 ; Don't convert (sext {...,+,...}) to {sext(...),+,sext(...)} in cases
25 %2 = sext i9 %1 to i64 ; <i64> [#uses=1]
29 %6 = sext i7 %0 to i64 ; <i64> [#uses=1]
48 %2 = sext i9 %1 to i64 ; <i64> [#uses=1]
[all …]
Dno-wrap-add-exprs.ll63 %t0.sext = sext i8 %t0 to i16
64 %t1.sext = sext i8 %t1 to i16
65 ; CHECK: %t0.sext = sext i8 %t0 to i16
67 ; CHECK: %t1.sext = sext i8 %t1 to i16
77 %q0.sext = sext i8 %q0 to i16
78 %q1.sext = sext i8 %q1 to i16
79 ; CHECK: %q0.sext = sext i8 %q0 to i16
80 ; CHECK-NEXT: --> (sext i8 (1 + %len_norange) to i16) U: [-128,128) S: [-128,128)
81 ; CHECK: %q1.sext = sext i8 %q1 to i16
82 ; CHECK-NEXT: --> (sext i8 (2 + %len_norange) to i16) U: [-128,128) S: [-128,128)
/external/llvm/test/Transforms/InstCombine/
Dsext.ll11 %s = sext i32 %t to i64
20 %s = sext i32 %t to i64
29 %s = sext i32 %t to i64
38 %s = sext i32 %t to i64
47 %s = sext i32 %t to i64
56 %s = sext i32 %t to i64
65 %s = sext i32 %u to i64
75 %n = sext i16 %s to i32
88 %t2 = sext i16 %t to i32
109 %b = sext i8 %a to i32
[all …]
/external/llvm/test/Analysis/Delinearization/
Dhimeno_1.ll29 …sext i32 %a.deps to i64) * (1 + (sext i32 %a.cols to i64))) + %a.base),+,(4 * (sext i32 %a.deps to…
31 ; CHECK: ArrayDecl[UnknownSize][(sext i32 %a.cols to i64)][(sext i32 %a.deps to i64)] with elements…
41 %p.rows.sext = sext i32 %p.rows.sub to i64
45 %p.cols.sext = sext i32 %p.cols.sub to i64
49 %p.deps.sext = sext i32 %p.deps.sub to i64
64 %a.cols.sext = sext i32 %a.cols to i64
65 %a.deps.sext = sext i32 %a.deps to i64
70 %tmp1 = mul nsw i64 %a.cols.sext, %i
72 %tmp3 = mul i64 %tmp2, %a.deps.sext
77 %k.exitcond = icmp eq i64 %k.inc, %p.deps.sext
[all …]
Dhimeno_2.ll29 …sext i32 %a.deps to i64) * (1 + (sext i32 %a.cols to i64))) + %a.base),+,(4 * (sext i32 %a.deps to…
31 ; CHECK: ArrayDecl[UnknownSize][(sext i32 %a.cols to i64)][(sext i32 %a.deps to i64)] with elements…
41 %p.rows.sext = sext i32 %p.rows.sub to i64
45 %p.cols.sext = sext i32 %p.cols.sub to i64
49 %p.deps.sext = sext i32 %p.deps.sub to i64
52 %a.cols.sext = sext i32 %a.cols to i64
55 %a.deps.sext = sext i32 %a.deps to i64
70 %tmp1 = mul nsw i64 %a.cols.sext, %i
72 %tmp3 = mul i64 %tmp2, %a.deps.sext
77 %k.exitcond = icmp eq i64 %k.inc, %p.deps.sext
[all …]
/external/llvm/test/Analysis/CostModel/PowerPC/
Dext.ll7 ; CHECK: cost of 1 {{.*}} sext
8 %v1 = sext i16 undef to i32
10 ; CHECK: cost of 1 {{.*}} sext
11 %v2 = sext <2 x i16> undef to <2 x i32>
13 ; CHECK: cost of 1 {{.*}} sext
14 %v3 = sext <4 x i16> undef to <4 x i32>
16 ; CHECK: cost of 112 {{.*}} sext
17 %v4 = sext <8 x i16> undef to <8 x i32>
/external/llvm/test/CodeGen/XCore/
Dsext.ll4 %2 = sext i1 %1 to i32
8 ; CHECK: sext r0, 1
12 %2 = sext i2 %1 to i32
16 ; CHECK: sext r0, 2
20 %2 = sext i8 %1 to i32
24 ; CHECK: sext r0, 8
28 %2 = sext i16 %1 to i32
32 ; CHECK: sext r0, 16
/external/llvm/test/CodeGen/AArch64/
Darm64-neon-compare-instructions.ll6 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
13 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
20 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
27 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
34 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
41 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
48 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
56 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
64 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
72 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
[all …]
/external/llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/
Dsplit-gep.ll22 %idxprom = sext i32 %add to i64
29 ; We should be able to trace into sext(a + b) if a + b is non-negative
35 %1 = sext i32 %0 to i64 ; inbound sext(i + 1) = sext(i) + 1
37 ; However, inbound sext(j + -2) != sext(j) + -2, e.g., j = INT_MIN
38 %3 = sext i32 %2 to i64
45 ; CHECK: sext
49 ; We should be able to trace into sext/zext if it can be distributed to both
50 ; operands, e.g., sext (add nsw a, b) == add nsw (sext a), (sext b)
53 ; gep base, a + sext(b +nsw 1), c + zext(d +nuw 1)
55 ; gep base, a + sext(b), c + zext(d); gep ..., 1 * 32 + 1
[all …]
/external/llvm/test/Transforms/IndVarSimplify/
D2009-04-14-shorten_iv_vars.ll1 ; RUN: opt < %s -indvars -S | not grep "sext"
20 %2 = sext i32 %i.0.reg2mem.0 to i64 ; <i64> [#uses=1]
24 %6 = sext i32 %i.0.reg2mem.0 to i64 ; <i64> [#uses=1]
28 %10 = sext i32 %i.0.reg2mem.0 to i64 ; <i64> [#uses=1]
35 %16 = sext i32 %15 to i64 ; <i64> [#uses=1]
40 %21 = sext i32 %20 to i64 ; <i64> [#uses=1]
44 %25 = sext i32 %13 to i64 ; <i64> [#uses=1]
51 %31 = sext i32 %30 to i64 ; <i64> [#uses=1]
56 %36 = sext i32 %35 to i64 ; <i64> [#uses=1]
60 %40 = sext i32 %28 to i64 ; <i64> [#uses=1]
[all …]
Delim-extend.ll6 ; IV rewrite only removes one sext. WidenIVs removes all three.
11 ; CHECK-NOT: sext
16 %preofs = sext i32 %iv to i64
20 %postofs = sext i32 %postiv to i64
24 %postofsnsw = sext i32 %postivnsw to i64
43 ; CHECK-NOT: sext
48 %preofs = sext i32 %iv to i64
52 %postofs = sext i32 %postiv to i64
56 %postofsnsw = sext i32 %postivnsw to i64
80 ; CHECK-NOT: sext
[all …]
/external/llvm/test/CodeGen/SystemZ/
Dint-conv-05.ll11 %ext = sext i16 %half to i32
21 %ext = sext i16 %half to i32
31 %ext = sext i16 %half to i32
42 %ext = sext i16 %half to i32
53 %ext = sext i16 %half to i32
64 %ext = sext i16 %half to i32
77 %ext = sext i16 %half to i32
88 %ext = sext i16 %half to i32
99 %ext = sext i16 %half to i32
112 %ext = sext i16 %half to i32
[all …]
Dint-conv-03.ll11 %ext = sext i8 %byte to i64
21 %ext = sext i8 %byte to i64
31 %ext = sext i8 %byte to i64
42 %ext = sext i8 %byte to i64
55 %ext = sext i8 %byte to i64
66 %ext = sext i8 %byte to i64
77 %ext = sext i8 %byte to i64
90 %ext = sext i8 %byte to i64
103 %ext = sext i8 %byte to i64
147 %ext0 = sext i8 %trunc0 to i64
[all …]
Dint-conv-07.ll11 %ext = sext i16 %half to i64
21 %ext = sext i16 %half to i64
31 %ext = sext i16 %half to i64
42 %ext = sext i16 %half to i64
55 %ext = sext i16 %half to i64
66 %ext = sext i16 %half to i64
77 %ext = sext i16 %half to i64
90 %ext = sext i16 %half to i64
103 %ext = sext i16 %half to i64
147 %ext0 = sext i16 %trunc0 to i64
[all …]
Dint-conv-01.ll11 %ext = sext i8 %byte to i32
21 %ext = sext i8 %byte to i32
31 %ext = sext i8 %byte to i32
42 %ext = sext i8 %byte to i32
55 %ext = sext i8 %byte to i32
66 %ext = sext i8 %byte to i32
77 %ext = sext i8 %byte to i32
90 %ext = sext i8 %byte to i32
103 %ext = sext i8 %byte to i32
147 %ext0 = sext i8 %trunc0 to i32
[all …]

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