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Searched refs:shuf (Results 1 – 25 of 25) sorted by relevance

/external/llvm/test/Analysis/CostModel/X86/
Dreduction.ll7 …%rdx.shuf = shufflevector <4 x float> %rdx, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 undef,…
8 %bin.rdx = fadd <4 x float> %rdx, %rdx.shuf
22 %rdx.shuf = shufflevector <8 x i32> %rdx, <8 x i32> undef,
25 %bin.rdx = add <8 x i32> %rdx, %rdx.shuf
26 %rdx.shuf.2 = shufflevector <8 x i32> %bin.rdx, <8 x i32> undef,
29 %bin.rdx.2 = add <8 x i32> %bin.rdx, %rdx.shuf.2
30 %rdx.shuf.3 = shufflevector <8 x i32> %bin.rdx.2, <8 x i32> undef,
33 %bin.rdx.3 = add <8 x i32> %bin.rdx.2, %rdx.shuf.3
43 %rdx.shuf.0.0 = shufflevector <4 x float> %rdx, <4 x float> undef,
45 %rdx.shuf.0.1 = shufflevector <4 x float> %rdx, <4 x float> undef,
[all …]
/external/llvm/test/CodeGen/X86/
Dsse-scalar-fp-arith-unary.ll21 %shuf = shufflevector <4 x float> %y, <4 x float> %x, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
22 ret <4 x float> %shuf
36 %shuf = shufflevector <4 x float> %y, <4 x float> %x, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
37 ret <4 x float> %shuf
51 %shuf = shufflevector <4 x float> %y, <4 x float> %x, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
52 ret <4 x float> %shuf
66 %shuf = shufflevector <2 x double> %y, <2 x double> %x, <2 x i32> <i32 0, i32 3>
67 ret <2 x double> %shuf
Dvec_int_to_fp.ll50 %shuf = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
51 %cvt = sitofp <2 x i32> %shuf to <2 x double>
67 %shuf = shufflevector <4 x double> %cvt, <4 x double> undef, <2 x i32> <i32 0, i32 1>
68 ret <2 x double> %shuf
84 %shuf = shufflevector <8 x i16> %a, <8 x i16> undef, <2 x i32> <i32 0, i32 1>
85 %cvt = sitofp <2 x i16> %shuf to <2 x double>
111 %shuf = shufflevector <8 x double> %cvt, <8 x double> undef, <2 x i32> <i32 0, i32 1>
112 ret <2 x double> %shuf
129 %shuf = shufflevector <16 x i8> %a, <16 x i8> undef, <2 x i32> <i32 0, i32 1>
130 %cvt = sitofp <2 x i8> %shuf to <2 x double>
[all …]
Dextractelement-shuffle.ll10 %shuf = shufflevector <2 x i64> %val1, <2 x i64> %val2, <2 x i32> <i32 0, i32 3>
11 %bit = bitcast <2 x i64> %shuf to <4 x i32>
Dvec_split.ll71 %rdx.shuf = shufflevector <2 x i128> %add, <2 x i128> undef, <2 x i32> <i32 undef, i32 0>
72 %bin.rdx = add <2 x i128> %add, %rdx.shuf
Dsse-scalar-fp-arith.ll434 %shuf = shufflevector <4 x float> %ins, <4 x float> %a, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
435 ret <4 x float> %shuf
452 %shuf = shufflevector <4 x float> %ins, <4 x float> %a, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
453 ret <4 x float> %shuf
470 %shuf = shufflevector <4 x float> %ins, <4 x float> %a, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
471 ret <4 x float> %shuf
488 %shuf = shufflevector <4 x float> %ins, <4 x float> %a, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
489 ret <4 x float> %shuf
506 %shuf = shufflevector <2 x double> %ins, <2 x double> %a, <2 x i32> <i32 0, i32 3>
507 ret <2 x double> %shuf
[all …]
Dvec_return.ll12 ; CHECK-NOT: shuf
Dvec_fp_to_int.ll510 %shuf = shufflevector <4 x float> %a, <4 x float> undef, <2 x i32> <i32 0, i32 1>
511 %cvt = fptosi <2 x float> %shuf to <2 x i64>
537 %shuf = shufflevector <4 x i64> %cvt, <4 x i64> undef, <2 x i32> <i32 0, i32 1>
538 ret <2 x i64> %shuf
594 %shuf = shufflevector <8 x float> %a, <8 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
595 %cvt = fptosi <4 x float> %shuf to <4 x i64>
638 %shuf = shufflevector <8 x i64> %cvt, <8 x i64> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
639 ret <4 x i64> %shuf
733 %shuf = shufflevector <4 x float> %a, <4 x float> undef, <2 x i32> <i32 0, i32 1>
734 %cvt = fptoui <2 x float> %shuf to <2 x i64>
[all …]
Davx-vzeroupper.ll94 …%shuf = shufflevector <4 x float> %a, <4 x float> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4…
97 %call = call <8 x float> @do_avx(<8 x float> %shuf) nounwind
Dwiden_shuffle-1.ll7 define void @shuf(<3 x float>* %dst.addr, <3 x float> %src1,<3 x float> %src2) nounwind {
8 ; CHECK-LABEL: shuf:
Dssse3-intrinsics-fast-isel.ll71 …%shuf = shufflevector <16 x i8> %arg0, <16 x i8> %arg1, <16 x i32> <i32 2, i32 3, i32 4, i32 5, i3…
72 %res = bitcast <16 x i8> %shuf to <2 x i64>
Davx512vl-intrinsics.ll4543 declare <8 x float> @llvm.x86.avx512.mask.shuf.f32x4.256(<8 x float>, <8 x float>, i32, <8 x float>…
4559 …%res = call <8 x float> @llvm.x86.avx512.mask.shuf.f32x4.256(<8 x float> %x0, <8 x float> %x1, i32…
4560 …%res1 = call <8 x float> @llvm.x86.avx512.mask.shuf.f32x4.256(<8 x float> %x0, <8 x float> %x1, i3…
4561 …%res2 = call <8 x float> @llvm.x86.avx512.mask.shuf.f32x4.256(<8 x float> %x0, <8 x float> %x1, i3…
4567 declare <4 x double> @llvm.x86.avx512.mask.shuf.f64x2.256(<4 x double>, <4 x double>, i32, <4 x dou…
4583 …%res = call <4 x double> @llvm.x86.avx512.mask.shuf.f64x2.256(<4 x double> %x0, <4 x double> %x1, …
4584 …%res1 = call <4 x double> @llvm.x86.avx512.mask.shuf.f64x2.256(<4 x double> %x0, <4 x double> %x1,…
4585 …%res2 = call <4 x double> @llvm.x86.avx512.mask.shuf.f64x2.256(<4 x double> %x0, <4 x double> %x1,…
4591 declare <8 x i32> @llvm.x86.avx512.mask.shuf.i32x4.256(<8 x i32>, <8 x i32>, i32, <8 x i32>, i8)
4604 …%res = call <8 x i32> @llvm.x86.avx512.mask.shuf.i32x4.256(<8 x i32> %x0, <8 x i32> %x1, i32 22, <…
[all …]
Davx512-intrinsics.ll5640 declare <16 x float> @llvm.x86.avx512.mask.shuf.f32x4(<16 x float>, <16 x float>, i32, <16 x float>…
5650 …%res = call <16 x float> @llvm.x86.avx512.mask.shuf.f32x4(<16 x float> %x0, <16 x float> %x1, i32 …
5651 …%res1 = call <16 x float> @llvm.x86.avx512.mask.shuf.f32x4(<16 x float> %x0, <16 x float> %x1, i32…
5656 declare <8 x double> @llvm.x86.avx512.mask.shuf.f64x2(<8 x double>, <8 x double>, i32, <8 x double>…
5669 …%res = call <8 x double> @llvm.x86.avx512.mask.shuf.f64x2(<8 x double> %x0, <8 x double> %x1, i32 …
5670 …%res1 = call <8 x double> @llvm.x86.avx512.mask.shuf.f64x2(<8 x double> %x0, <8 x double> %x1, i32…
5671 …%res2 = call <8 x double> @llvm.x86.avx512.mask.shuf.f64x2(<8 x double> %x0, <8 x double> %x1, i32…
5678 declare <16 x i32> @llvm.x86.avx512.mask.shuf.i32x4(<16 x i32>, <16 x i32>, i32, <16 x i32>, i16)
5688 …%res = call <16 x i32> @llvm.x86.avx512.mask.shuf.i32x4(<16 x i32> %x0, <16 x i32> %x1, i32 22, <1…
5689 …%res1 = call <16 x i32> @llvm.x86.avx512.mask.shuf.i32x4(<16 x i32> %x0, <16 x i32> %x1, i32 22, <…
[all …]
Dvector-shuffle-256-v8.ll2212 …%shuf = shufflevector <4 x i32> %alo, <4 x i32> %bhi, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4…
2213 ret <8 x i32> %shuf
Dvector-shuffle-256-v16.ll3326 …%shuf = shufflevector <8 x i16> %alo, <8 x i16> %bhi, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 …
3327 ret <16 x i16> %shuf
/external/llvm/test/CodeGen/AArch64/
Daarch64-minmaxv.ll10 …%rdx.shuf = shufflevector <16 x i8> %arr.load, <16 x i8> undef, <16 x i32> <i32 8, i32 9, i32 10, …
11 %rdx.minmax.cmp22 = icmp sgt <16 x i8> %arr.load, %rdx.shuf
12 …%rdx.minmax.select23 = select <16 x i1> %rdx.minmax.cmp22, <16 x i8> %arr.load, <16 x i8> %rdx.shuf
32 …%rdx.shuf = shufflevector <8 x i16> %rdx.minmax.select, <8 x i16> undef, <8 x i32> <i32 4, i32 5, …
33 %rdx.minmax.cmp23 = icmp sgt <8 x i16> %rdx.minmax.select, %rdx.shuf
34 …max.select24 = select <8 x i1> %rdx.minmax.cmp23, <8 x i16> %rdx.minmax.select, <8 x i16> %rdx.shuf
51 …%rdx.shuf = shufflevector <4 x i32> %rdx.minmax.select, <4 x i32> undef, <4 x i32> <i32 2, i32 3, …
52 %rdx.minmax.cmp18 = icmp sgt <4 x i32> %rdx.minmax.select, %rdx.shuf
53 …max.select19 = select <4 x i1> %rdx.minmax.cmp18, <4 x i32> %rdx.minmax.select, <4 x i32> %rdx.shuf
67 …%rdx.shuf = shufflevector <2 x i64> %rdx.minmax.select, <2 x i64> undef, <2 x i32> <i32 1, i32 und…
[all …]
Daarch64-addv.ll9 …%rdx.shuf = shufflevector <16 x i8> %bin.rdx0, <16 x i8> undef, <16 x i32> <i32 4, i32 5, i32 6, i…
10 %bin.rdx11 = add <16 x i8> %bin.rdx0, %rdx.shuf
23 …%rdx.shuf = shufflevector <8 x i16> %bin.rdx, <8 x i16> undef, <8 x i32> <i32 4, i32 5, i32 6, i32…
24 %bin.rdx11 = add <8 x i16> %bin.rdx, %rdx.shuf
37 …%rdx.shuf = shufflevector <4 x i32> %bin.rdx, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 undef,…
38 %bin.rdx11 = add <4 x i32> %bin.rdx, %rdx.shuf
69 …%rdx.shuf = shufflevector <8 x i32> %9, <8 x i32> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i3…
70 %bin.rdx = add <8 x i32> %9, %rdx.shuf
87 …%rdx.shuf = shufflevector <16 x i32> %bin.rdx0, <16 x i32> undef, <16 x i32> <i32 4, i32 5, i32 6,…
88 %bin.rdx11 = add <16 x i32> %bin.rdx0, %rdx.shuf
Darm64-vabs.ll149 …%rdx.shuf = shufflevector <16 x i16> %absel, <16 x i16> undef, <16 x i32> <i32 8, i32 9, i32 10, i…
150 %bin1.rdx = add <16 x i16> %absel, %rdx.shuf
173 …%rdx.shuf = shufflevector <8 x i32> %absel, <8 x i32> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7…
174 %bin.rdx = add <8 x i32> %absel, %rdx.shuf
/external/mesa3d/src/gallium/auxiliary/rtasm/
Drtasm_x86sse.c1166 unsigned char shuf) in sse_shufps() argument
1168 DUMP_RRI( dst, src, shuf ); in sse_shufps()
1171 emit_1ub(p, shuf); in sse_shufps()
1298 unsigned char shuf) in sse2_pshufd() argument
1300 DUMP_RRI( dst, src, shuf ); in sse2_pshufd()
1303 emit_1ub(p, shuf); in sse2_pshufd()
1309 unsigned char shuf) in sse2_pshuflw() argument
1311 DUMP_RRI( dst, src, shuf ); in sse2_pshuflw()
1314 emit_1ub(p, shuf); in sse2_pshuflw()
1320 unsigned char shuf) in sse2_pshufhw() argument
[all …]
Drtasm_x86sse.h242 unsigned char shuf );
244 unsigned char shuf );
246 unsigned char shuf );
304 unsigned char shuf );
/external/llvm/test/CodeGen/ARM/
Dshuffle.ll6 define <8 x i8> @shuf(<8 x i8> %a) nounwind readnone optsize ssp {
/external/mesa3d/src/mesa/x86/rtasm/
Dx86sse.h151 unsigned char shuf );
181 unsigned char shuf );
Dx86sse.c632 unsigned char shuf) in sse_shufps() argument
636 emit_1ub(p, shuf); in sse_shufps()
667 unsigned char shuf) in sse2_pshufd() argument
671 emit_1ub(p, shuf); in sse2_pshufd()
/external/llvm/test/Transforms/LoopVectorize/
Ddebugloc.ll17 ; CHECK: add <2 x i32> %{{.*}}, %rdx.shuf, !dbg ![[LOC2]]
/external/clang/test/
Dcxx-sections.data1168 26.5.4.3 [rand.adapt.shuf]