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Searched refs:sreg (Results 1 – 19 of 19) sorted by relevance

/external/llvm/test/CodeGen/NVPTX/
Denvreg.ll4 declare i32 @llvm.nvvm.read.ptx.sreg.envreg0()
5 declare i32 @llvm.nvvm.read.ptx.sreg.envreg1()
6 declare i32 @llvm.nvvm.read.ptx.sreg.envreg2()
7 declare i32 @llvm.nvvm.read.ptx.sreg.envreg3()
8 declare i32 @llvm.nvvm.read.ptx.sreg.envreg4()
9 declare i32 @llvm.nvvm.read.ptx.sreg.envreg5()
10 declare i32 @llvm.nvvm.read.ptx.sreg.envreg6()
11 declare i32 @llvm.nvvm.read.ptx.sreg.envreg7()
12 declare i32 @llvm.nvvm.read.ptx.sreg.envreg8()
13 declare i32 @llvm.nvvm.read.ptx.sreg.envreg9()
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Dldu-reg-plus-offset.ll19 declare i32 @llvm.nvvm.read.ptx.sreg.tid.x()
/external/v8/src/arm64/
Dsimulator-arm64.cc1630 case STR_s: MemoryWrite<float>(address, sreg(srcdst)); break; in LoadStoreHelper()
1759 MemoryWrite<float>(address, sreg(rt)); in LoadStorePairHelper()
1760 MemoryWrite<float>(address2, sreg(rt2)); in LoadStorePairHelper()
2225 case FCVTAS_ws: set_wreg(dst, FPToInt32(sreg(src), FPTieAway)); break; in VisitFPIntegerConvert()
2226 case FCVTAS_xs: set_xreg(dst, FPToInt64(sreg(src), FPTieAway)); break; in VisitFPIntegerConvert()
2229 case FCVTAU_ws: set_wreg(dst, FPToUInt32(sreg(src), FPTieAway)); break; in VisitFPIntegerConvert()
2230 case FCVTAU_xs: set_xreg(dst, FPToUInt64(sreg(src), FPTieAway)); break; in VisitFPIntegerConvert()
2234 set_wreg(dst, FPToInt32(sreg(src), FPNegativeInfinity)); in VisitFPIntegerConvert()
2237 set_xreg(dst, FPToInt64(sreg(src), FPNegativeInfinity)); in VisitFPIntegerConvert()
2246 set_wreg(dst, FPToUInt32(sreg(src), FPNegativeInfinity)); in VisitFPIntegerConvert()
[all …]
Dsimulator-arm64.h420 float sreg(unsigned code) const {
438 case kSRegSizeInBits: return sreg(code);
/external/llvm/test/Analysis/DivergenceAnalysis/NVPTX/
Ddiverge.ll10 %tid = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
32 %tid = call i32 @llvm.nvvm.read.ptx.sreg.tid.y()
53 %tid = call i32 @llvm.nvvm.read.ptx.sreg.tid.z()
125 %tid = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
161 %tid = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
192 %tid = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
208 declare i32 @llvm.nvvm.read.ptx.sreg.tid.x()
209 declare i32 @llvm.nvvm.read.ptx.sreg.tid.y()
210 declare i32 @llvm.nvvm.read.ptx.sreg.tid.z()
/external/v8/src/arm/
Dsimulator-arm.h170 void set_s_register_from_float(int sreg, const float flt) { in set_s_register_from_float() argument
171 SetVFPRegister<float, 1>(sreg, flt); in set_s_register_from_float()
174 float get_float_from_s_register(int sreg) { in get_float_from_s_register() argument
175 return GetFromVFPRegister<float, 1>(sreg); in get_float_from_s_register()
178 void set_s_register_from_sinteger(int sreg, const int sint) { in set_s_register_from_sinteger() argument
179 SetVFPRegister<int, 1>(sreg, sint); in set_s_register_from_sinteger()
182 int get_sinteger_from_s_register(int sreg) { in get_sinteger_from_s_register() argument
183 return GetFromVFPRegister<int, 1>(sreg); in get_sinteger_from_s_register()
Dsimulator-arm.cc1003 void Simulator::set_s_register(int sreg, unsigned int value) { in set_s_register() argument
1004 DCHECK((sreg >= 0) && (sreg < num_s_registers)); in set_s_register()
1005 vfp_registers_[sreg] = value; in set_s_register()
1009 unsigned int Simulator::get_s_register(int sreg) const { in get_s_register()
1010 DCHECK((sreg >= 0) && (sreg < num_s_registers)); in get_s_register()
1011 return vfp_registers_[sreg]; in get_s_register()
/external/llvm/docs/
DNVPTXUsage.rst196 '``llvm.nvvm.read.ptx.sreg.*``'
204 declare i32 @llvm.nvvm.read.ptx.sreg.tid.x()
205 declare i32 @llvm.nvvm.read.ptx.sreg.tid.y()
206 declare i32 @llvm.nvvm.read.ptx.sreg.tid.z()
207 declare i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
208 declare i32 @llvm.nvvm.read.ptx.sreg.ntid.y()
209 declare i32 @llvm.nvvm.read.ptx.sreg.ntid.z()
210 declare i32 @llvm.nvvm.read.ptx.sreg.ctaid.x()
211 declare i32 @llvm.nvvm.read.ptx.sreg.ctaid.y()
212 declare i32 @llvm.nvvm.read.ptx.sreg.ctaid.z()
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/external/clang/include/clang/StaticAnalyzer/Core/PathSensitive/
DMemRegion.h534 CodeTextRegion(const MemRegion *sreg, Kind k) : TypedRegion(sreg, k) {} in CodeTextRegion() argument
548 FunctionTextRegion(const NamedDecl *fd, const MemRegion* sreg) in FunctionTextRegion() argument
549 : CodeTextRegion(sreg, FunctionTextRegionKind), FD(fd) { in FunctionTextRegion()
598 AnalysisDeclContext *ac, const MemRegion* sreg) in BlockTextRegion() argument
599 : CodeTextRegion(sreg, BlockTextRegionKind), BD(bd), AC(ac), locTy(lTy) {} in BlockTextRegion()
640 unsigned count, const MemRegion *sreg) in BlockDataRegion() argument
641 : TypedRegion(sreg, BlockDataRegionKind), BC(bc), LC(lc), in BlockDataRegion()
716 SymbolicRegion(const SymbolRef s, const MemRegion* sreg) in SymbolicRegion() argument
717 : SubRegion(sreg, SymbolicRegionKind), sym(s) {} in SymbolicRegion()
746 StringRegion(const StringLiteral* str, const MemRegion* sreg) in StringRegion() argument
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/external/vixl/src/vixl/a64/
Dsimulator-a64.cc1120 case STR_s: Memory::Write<float>(address, sreg(srcdst)); break; in LoadStoreHelper()
1227 Memory::Write<float>(address, sreg(rt)); in LoadStorePairHelper()
1228 Memory::Write<float>(address2, sreg(rt2)); in LoadStorePairHelper()
1919 case FCVTAS_ws: set_wreg(dst, FPToInt32(sreg(src), FPTieAway)); break; in VisitFPIntegerConvert()
1920 case FCVTAS_xs: set_xreg(dst, FPToInt64(sreg(src), FPTieAway)); break; in VisitFPIntegerConvert()
1923 case FCVTAU_ws: set_wreg(dst, FPToUInt32(sreg(src), FPTieAway)); break; in VisitFPIntegerConvert()
1924 case FCVTAU_xs: set_xreg(dst, FPToUInt64(sreg(src), FPTieAway)); break; in VisitFPIntegerConvert()
1928 set_wreg(dst, FPToInt32(sreg(src), FPNegativeInfinity)); in VisitFPIntegerConvert()
1931 set_xreg(dst, FPToInt64(sreg(src), FPNegativeInfinity)); in VisitFPIntegerConvert()
1940 set_wreg(dst, FPToUInt32(sreg(src), FPNegativeInfinity)); in VisitFPIntegerConvert()
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Dsimulator-a64.h886 float sreg(unsigned code) const { in sreg() function
/external/llvm/include/llvm/IR/
DIntrinsicsNVVM.td921 "llvm.nvvm.read.ptx.sreg.envreg0">,
925 "llvm.nvvm.read.ptx.sreg.envreg1">,
929 "llvm.nvvm.read.ptx.sreg.envreg2">,
933 "llvm.nvvm.read.ptx.sreg.envreg3">,
937 "llvm.nvvm.read.ptx.sreg.envreg4">,
941 "llvm.nvvm.read.ptx.sreg.envreg5">,
945 "llvm.nvvm.read.ptx.sreg.envreg6">,
949 "llvm.nvvm.read.ptx.sreg.envreg7">,
953 "llvm.nvvm.read.ptx.sreg.envreg8">,
957 "llvm.nvvm.read.ptx.sreg.envreg9">,
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/external/vixl/test/
Dtest-utils-a64.h101 inline float sreg(unsigned code) const { in sreg() function
Dtest-utils-a64.cc166 return EqualFP32(expected, core, core->sreg(fpreg.code())); in EqualFP32()
/external/v8/test/cctest/
Dtest-utils-arm64.h80 inline float sreg(unsigned code) const { in sreg() function
Dtest-utils-arm64.cc134 return EqualFP32(expected, core, core->sreg(fpreg.code())); in EqualFP32()
/external/valgrind/VEX/priv/
Dguest_x86_toIR.c484 static Int segmentGuestRegOffset ( UInt sreg ) in segmentGuestRegOffset() argument
486 switch (sreg) { in segmentGuestRegOffset()
561 static IRExpr* getSReg ( UInt sreg ) in getSReg() argument
563 return IRExpr_Get( segmentGuestRegOffset(sreg), Ity_I16 ); in getSReg()
566 static void putSReg ( UInt sreg, IRExpr* e ) in putSReg() argument
569 stmt( IRStmt_Put( segmentGuestRegOffset(sreg), e ) ); in putSReg()
1290 static const HChar* nameSReg ( UInt sreg ) in nameSReg() argument
1292 switch (sreg) { in nameSReg()
1423 Int sreg; in handleSegOverride() local
1432 case 0x3E: sreg = R_DS; break; in handleSegOverride()
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Dguest_amd64_toIR.c2156 static const HChar* nameSReg ( UInt sreg ) in nameSReg() argument
2158 switch (sreg) { in nameSReg()
/external/clang/lib/StaticAnalyzer/Core/
DMemRegion.cpp337 const MemRegion *sreg) { in ProfileRegion() argument
340 ID.AddPointer(sreg); in ProfileRegion()