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Searched refs:v16i16 (Results 1 – 25 of 25) sorted by relevance

/external/clang/test/CodeGen/
Dppc64-vector.c8 typedef short v16i16 __attribute__((vector_size (32))); typedef
10 struct v16i16 { v16i16 x; }; argument
43 v16i16 test_v16i16(v16i16 x) in test_v16i16()
49 struct v16i16 test_struct_v16i16(struct v16i16 x) in test_struct_v16i16()
/external/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp121 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence in getArithmeticInstrCost()
122 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence in getArithmeticInstrCost()
165 if (ISD == ISD::SHL && LT.second == MVT::v16i16 && in getArithmeticInstrCost()
194 { ISD::SHL, MVT::v16i16, 2 }, in getArithmeticInstrCost()
195 { ISD::SRL, MVT::v16i16, 4 }, in getArithmeticInstrCost()
196 { ISD::SRA, MVT::v16i16, 4 }, in getArithmeticInstrCost()
213 { ISD::SHL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. in getArithmeticInstrCost()
216 { ISD::SRL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. in getArithmeticInstrCost()
219 { ISD::SRA, MVT::v16i16, 10 }, // extend/vpsravd/pack sequence. in getArithmeticInstrCost()
225 { ISD::SDIV, MVT::v16i16, 16*20 }, in getArithmeticInstrCost()
[all …]
DX86CallingConv.td62 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
145 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
306 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
328 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
369 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCPassIndirect<i64>>,
411 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
486 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
502 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
521 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
616 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
[all …]
DX86InstrSSE.td350 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (iPTR 0))),
351 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
367 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
426 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
432 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
437 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
442 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
444 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
448 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
449 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
[all …]
DX86ISelLowering.cpp1059 setOperationAction(ISD::ROTL, MVT::v16i16, Custom); in X86TargetLowering()
1066 addRegisterClass(MVT::v16i16, &X86::VR256RegClass); in X86TargetLowering()
1118 setOperationAction(ISD::SRL, MVT::v16i16, Custom); in X86TargetLowering()
1121 setOperationAction(ISD::SHL, MVT::v16i16, Custom); in X86TargetLowering()
1124 setOperationAction(ISD::SRA, MVT::v16i16, Custom); in X86TargetLowering()
1128 setOperationAction(ISD::SETCC, MVT::v16i16, Custom); in X86TargetLowering()
1138 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom); in X86TargetLowering()
1141 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom); in X86TargetLowering()
1144 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom); in X86TargetLowering()
1150 setOperationAction(ISD::CTPOP, MVT::v16i16, Custom); in X86TargetLowering()
[all …]
DX86RegisterInfo.td451 def VR256 : RegisterClass<"X86", [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64],
476 def VR256X : RegisterClass<"X86", [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64],
DX86InstrAVX512.td444 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
450 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
455 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
460 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
462 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
466 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
467 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
468 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
469 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
470 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
[all …]
DX86InstrFragmentsSIMD.td861 def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>;
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h82 v16i16 = 34, // 16 x i16 enumerator
251 SimpleTy == MVT::v32i8 || SimpleTy == MVT::v16i16 || in is256BitVector()
331 case v16i16: in getVectorElementType()
384 case v16i16: in getVectorNumElements()
484 case v16i16: in getSizeInBits()
611 if (NumElements == 16) return MVT::v16i16; in getVectorVT()
DValueTypes.td59 def v16i16 : ValueType<256, 34>; // 16 x i16 vector value
/external/llvm/test/CodeGen/X86/
Davx2-cmp.ll18 define <16 x i16> @v16i16-cmp(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
46 define <16 x i16> @v16i16-cmpeq(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
Davx-cmp.ll72 define <16 x i16> @v16i16-cmp(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
116 define <16 x i16> @v16i16-cmpeq(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
Dvector-popcnt-256.ll140 %out = call <16 x i16> @llvm.ctpop.v16i16(<16 x i16> %in)
203 …%out = call <16 x i16> @llvm.ctpop.v16i16(<16 x i16> <i16 256, i16 -1, i16 0, i16 255, i16 -65536,…
218 declare <16 x i16> @llvm.ctpop.v16i16(<16 x i16>)
Dbswap-vector.ll114 declare <16 x i16> @llvm.bswap.v16i16(<16 x i16>)
157 %r = call <16 x i16> @llvm.bswap.v16i16(<16 x i16> %v)
328 %bs1 = call <16 x i16> @llvm.bswap.v16i16(<16 x i16> %v)
329 %bs2 = call <16 x i16> @llvm.bswap.v16i16(<16 x i16> %bs1)
424 …%r = call <16 x i16> @llvm.bswap.v16i16(<16 x i16> <i16 0, i16 1, i16 -1, i16 2, i16 -3, i16 4, i1…
Dvector-tzcnt-256.ll295 %out = call <16 x i16> @llvm.cttz.v16i16(<16 x i16> %in, i1 0)
353 %out = call <16 x i16> @llvm.cttz.v16i16(<16 x i16> %in, i1 -1)
496 …%out = call <16 x i16> @llvm.cttz.v16i16(<16 x i16> <i16 256, i16 -1, i16 0, i16 255, i16 -65536, …
505 …%out = call <16 x i16> @llvm.cttz.v16i16(<16 x i16> <i16 256, i16 -1, i16 0, i16 255, i16 -65536, …
529 declare <16 x i16> @llvm.cttz.v16i16(<16 x i16>, i1)
Dvector-lzcnt-256.ll533 %out = call <16 x i16> @llvm.ctlz.v16i16(<16 x i16> %in, i1 0)
693 %out = call <16 x i16> @llvm.ctlz.v16i16(<16 x i16> %in, i1 -1)
1458 …%out = call <16 x i16> @llvm.ctlz.v16i16(<16 x i16> <i16 256, i16 -1, i16 0, i16 255, i16 -65536, …
1477 …%out = call <16 x i16> @llvm.ctlz.v16i16(<16 x i16> <i16 256, i16 -1, i16 0, i16 255, i16 -65536, …
1521 declare <16 x i16> @llvm.ctlz.v16i16(<16 x i16>, i1)
/external/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp122 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 }, in getCastInstrCost()
123 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 }, in getCastInstrCost()
149 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 8 }, in getCastInstrCost()
150 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 8 } in getCastInstrCost()
/external/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp209 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, in getCastInstrCost()
210 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, in getCastInstrCost()
391 { ISD::SELECT, MVT::v16i1, MVT::v16i16, 16 }, in getCmpSelInstrCost()
/external/llvm/lib/IR/
DValueTypes.cpp161 case MVT::v16i16: return "v16i16"; in getEVTString()
239 case MVT::v16i16: return VectorType::get(Type::getInt16Ty(Context), 16); in getTypeForEVT()
/external/llvm/utils/TableGen/
DCodeGenTarget.cpp94 case MVT::v16i16: return "MVT::v16i16"; in getEnumName()
/external/llvm/lib/Target/X86/InstPrinter/
DX86InstComments.cpp64 DstVT = MVT::v16i16; in getZeroExtensionTypes()
/external/llvm/include/llvm/IR/
DIntrinsics.td181 def llvm_v16i16_ty : LLVMType<v16i16>; // 16 x i16
/external/llvm/lib/Target/AMDGPU/
DSIISelLowering.cpp157 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v16i16, Expand); in SITargetLowering()
169 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Expand); in SITargetLowering()
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp191 if (LocVT == MVT::v4i64 || LocVT == MVT::v8i32 || LocVT == MVT::v16i16 || in CC_Hexagon_VarArg()
257 if (LocVT == MVT::v8i32 || LocVT == MVT::v16i16 || LocVT == MVT::v32i8) { in CC_Hexagon()
/external/llvm/test/Analysis/CostModel/X86/
Dvshift-shl-cost.ll474 ; v16i16 and v8i32 shift left by non-uniform constant are lowered into